International Business Machines Corporation

Mark J Wolski

Eric Francis Robinson

Jason Alan Cox

Dennis P Cheney

Robert J Yagley

Andrew E Petruski

Thuong Quang Truong

Stefan P Jackowski

Kevin C Lin

James T Moyer

Praveen Karandikar

Robert John Dorsey

Kevin C K Lin

Josephine A Boston

Peter N James

Gregory S Ulsh

Richard C Lang

Keith A DeWeese

Richard L Hester

Robert G Rush

Ensuring forward progress of token-required cache operations in a shared cache, including: snooping an instruction to execute a token-required cache operation; determining if a snoop machine is available and if the snoop machine is set to a reservation state; if the snoop machine is available and the snoop machine is in the reservation state, determining whether the instruction to execute the token-required cache operation owns a token or is a joint instruction; if the instruction is a joint instruction, instructing the operation to retry; if the instruction to execute the token-required cache operation owns a token, dispatching a cache controller; determining whether all required cache controllers of relevant compute nodes are available to execute the instruction; executing the instruction if the required cache controllers are available otherwise not executing the instruction.

Ensuring forward progress of token-required cache operations in a shared cache

Acquiring access to a token controlled system resource, including: receiving, by a token broker, a command that requires access to the token controlled system resource, where the token broker is automated computing machinery for acquiring tokens and distributing the command to the token controlled system resource for execution; identifying, by the token broker, a first need state, the first need state indicating that the token broker requires access to the token controlled system resource to which the token broker does not possess a token; requesting, by the token broker, a configurable number of tokens to gain access to the token controlled system resource, without dispatching an operation handler for executing the command until at least one token is acquired; assigning, by the token broker, an acquired token to the operation handler; and dispatching, by the token broker, the operation handler and its assigned token for executing the command.

Acquiring access to a token controlled system resource

An L2 cache, method and computer program product for transferring an inbound bus operation to a processor side handling machine. The method includes a bus operation handling machine accepting the inbound bus operation received over a system interconnect, the bus operation handling machine identifying a demand operation of the processor side handling machine that will complete the bus operation, the bus operation handling machine sending the identified demand operation to the processor side handling machine, and the processor side handling machine performing the identified demand operation.

Transfer of bus-based operations to demand-side machines

Methods, apparatuses, and computer program products are disclosed for cache management. Embodiments include receiving, by a cache controller, a request to insert a new cache line into a cache; determining, by the cache controller, whether the new cache line is associated with a forced injection; in response to determining that the new cache line is associated with a forced injection, accepting, by the cache controller, the insertion of the new cache line into the cache; and in response to determining that the new cache line is not associated with a forced injection, determining, by the cache controller, whether to accept the insertion of the new cache line based on a comparison of an address of the new cache line to a predefined range of addresses.

Managing unforced injections of cache lines into a cache utilizing predetermined address ranges

A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.

Efficient and flexible trace trigger handling for non-concurrent events

A system and method for verifying the integrity of control information and informational data. One embodiment of the present invention verifies the integrity of control information received from a host computer, and verifies the integrity of this information as it is transmitted throughout the present invention. Another embodiment of the present invention contemplates verifying the integrity of informational data sent from a host computer, verifying the integrity of informational data as it is transmitted throughout the present invention, generating a CRC based upon the informational data and control information, and transmitting the informational data, control information and corresponding CRC to a storage device.

System and method for improving the integrity of control information

A system and method for striping data to multiple storage devices is provided. One embodiment of the present invention sequentially gates data to a plurality of buffers, wherein only those buffers corresponding to storage devices in use are induced to gate in data. The data is then sent to the storage devices in parallel. Other embodiments further include the use of striping buffers alternatingly used to gate in data, and transfer data to the storage devices.

Data storage buffer system and method

A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.

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Apex, NC, United States of America

Mark J Wolski