Alcatel USA Sourcing, L.p.

Mark J Nietubyc

Werner L Heissenhuber

Stephen A Deschaine

Manouchehr Entezari

Michael H Jette

Edward P Traupman

Mark W Berry

Clemente G Garcia

Henry K Lee

Shaun Bennett

A centrally-managed switch for interconnecting a plurality of digital signals through a plurality of selectable switch ports and controlled by a central management unit includes a cross-connect having a plurality of plesiochronous primary rate signal ports for receiving a plurality of plesiochronous primary rate signals, each plesiochronous primary rate signal comprising a plurality of channels, the cross-connect operable to switch ones of the channels of an originating plesiochronous primary rate signal to a destination plesiochronous primary rate signal. The invention further comprises an add/drop multiplexer comprising a plurality of synchronous primary rate signal ports coupled to the second plurality of plesiochronous primary rate signal ports of the cross-connect and operable to receive a plurality of synchronous high-speed signals, each synchronous high-speed signal comprising a plurality of synchronous primary rate signals, the add/drop multiplexer operable to remove ones of the synchronous primary rate signals from an originating synchronous high-speed signal and to add synchronous primary rate signals to a destination high speed synchronous signal. The cross-connect and add/drop multiplexer receive commands from the central management unit, the central management unit operable to generate commands to configure the switch for switching of data between synchronous high speed signals at a channel level in the cross-connect, and to generate commands to configure the switch for insertion of data from an originating plesiochronous primary rate signal into a destination synchronous high-speed signal.

System and method for centrally-managing switching functions

An interface unit (12) for interfacing a digital loop carrier (16) to a digital cross-connect (14) comprises a control interface (22) coupled between the digital cross-connect (14) and digital loop carrier (16) for conversion and communication of control messages therebetween. A timing interface (32) is further coupled between the digital cross-connect (14) and digital loop carrier (16) for generally synchronizing the operations thereof. Further, a matrix interface (30) is coupled between the digital cross-connect (14) and digital loop carrier (16) for converting data rates and formats of data in the digital cross-connect (14) and digital loop carrier (16), so that network signals received by the digital loop carrier (16) are converted from a first format to a second format and communicated by the matrix interface (30) to the digital cross-connect (14) for cross-connection, and cross-connected data are converted from the second format to the first format and communicated to the digital loop carrier (16).

Digital cross-connect system to digital loop carrier interface unit

Apparatus for redundancy circuit protection includes a controller (20), a plurality of circuits (22) coupled to the controller (20), and a redundancy switch (50) coupled between the plurality of circuits (22) and a network. The redundancy switch (50) is adapted for connecting or disconnecting selected ones of the plurality of circuits (22) to or from the network. In addition, a predetermined number of spare circuits (52) with similar functionality as the plurality of circuits (22) are coupled to the high density bank control unit (20), so that the redundancy switch (50) may connect or disconnect selected ones of the predetermined number of spare circuits (52) to the network and establish a transmission path from the controller (20) through the selected spare circuits (52) to the network.

Apparatus and method for circuit protection

Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

Apparatus and method for mapping high density E1 signals into a digital

Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of the first E1 signal are mapped into the space of a first DS1 signal in the logical space. The 8 DS0 signals of the first E1 signal are then mapped into the space of a second DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals may be mapped into the logical space of two DS1 signals in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

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Plano, TX, United States of America

Mark J Nietubyc