Lockheed Martin Corporation

Bae Systems Information and Electronic Systems Integration Inc.

Bae Systems, Inc.

Mark J Jones

John Walter Rapp

Larry Jackson

Troy Cherasaro

Scott C Willis

Chandan Mathur

Scott Hellenbach

Brent I Gouldey

Nicholas John Nagurny

Kenneth R Schulz

Joseph A Capizzi

Wendy S Normark

Robert James Howard

Jyun-Horng Fu

Joseph R Mayersak

Howard R Taylor

Robert J Varley

Stephen Melicher

Richard A Udicious

Joel J Fuster

Michael E Feeley

Various embodiments of the invention relate to enclosure assemblies housing at least one electronic board assembly and systems (e.g., missiles or unmanned vehicles) that may employ such enclosure assemblies. In an embodiment, an enclosure assembly includes an enclosure having an interior surface defining an interior space and an inner diameter. At least one electronic board assembly is positioned within the interior space and includes a first peripheral edge region and an opposing second peripheral edge region. The electronic board assembly extends diametrically so that the first and second peripheral edge regions are at least proximate to the interior surface. In another embodiment, a plurality of electronic board assemblies are positioned within the interior space and each extends generally along a respective non-diametric chord defined by the interior surface.

Enclosure assembly housing at least one electronic board assembly and systems using same

A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Pipeline accelerator having multiple pipeline units and related computing machine and method

Various embodiments of the invention relate to electronics modules, enclosure assemblies housing at least one such electronics module, and systems (e.g., missiles or unmanned vehicles) that may employ such enclosure assemblies. In one embodiment, an electronics module includes a first plate extending generally in a first plane, and a second plate spaced from the first plate and extending generally in a second plane. The electronics module further includes a plurality of electronic board assemblies each of which extends generally in a respective plane and is in thermal communication with at least one of the first and second plates. Each electronic board assembly may be positioned between the first and second plates and oriented so that the respective plane thereof is non-parallel relative to the first and second planes.

Electronics module, enclosure assembly housing same, and related systems and methods

A projectile system includes an enclosure, first and second propellants, and first and second projectiles. The first and second propellants are disposed within the enclosure. The first projectile is disposed within the enclosure between the first propellant and a first end of the enclosure, and is operable to exit the enclosure via the first end in response to detonation of the first charge. The second projectile is disposed within the enclosure between the second propellant and a second end of the enclosure, and is operable to exit the enclosure via the second end in response to the detonation of the second propellant.

Projectile accelerator and related vehicle and method

A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e.g., an FPGA) to take over for a failed second type of circuit (e.g., a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power.

Reconfigurable computing machine and related systems and methods

According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore server and a system-restore bus that allow the machine to periodically save the machine states in case of a failure. Such a computing machine has a fault-tolerant scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra 'space' than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.

Computing machine with redundancy and related systems and methods

A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is operable responsive to the first control signals to develop second control signals adapted to be applied to a memory subsystem to access desired storage locations within the memory subsystem.

Service layer architecture for memory access system and method

A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.

Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction

Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method

A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.

Programmable circuit and related computing machine and method

An under voltage lockout {overscore (RESET)} circuit is connected to the {overscore (RESET)} terminal of a EEPROM. The EEPROM is used in a system which may include a computer or processor and which may be used in space. The under voltage lockout {overscore (RESET)} circuit maybe an under voltage lockout circuit used on a LinFinity SG1526/B or a Unitrode UC1526 regulating pulse width modulator which maintain the {overscore (RESET)} voltage low at all values of power supply voltage source voltage less than a predetermined level. In one embodiment the under voltage lockout {overscore (RESET)} circuit output voltage does not have a &ldquo;floating voltage&rdquo; which rises to a level higher than its value when a comparator initially senses that a power supply voltage source voltage is less than the predetermined amount. This is a flat {overscore (RESET)} characteristic under voltage lockout. The {overscore (RESET)} circuit in combination with the EEPROM and computer has particular utility in space applications when a &ldquo;floating voltage&rdquo; may be undesirable and may cause failure in a satellite.

Method and apparatus for a voltage responsive RESET for EEPROM

Method and apparatus for a voltage responsive reset for EEPROM

A power transistor switched power supply connecting a power source to a capacitive load, including a circuit and method for limiting the inrush surge current through the power transistor. The control gate of a junction field effect transistor (JFET) is coupled between the conductive path of the power transistor and the load to sense voltage drop across the power transistor. The conductive controlled path of the JFET is connected to control the impedance of the power transistor. The JFET shunts some of the power transistor control terminal current during the on transition allowing the power transistor to only turn partially on for a period of time, thus limiting the current through the power transistor from the power source to the load. Because the inrush surge current is limited, the accompanying transient power source voltage drop is reduced with less impact to other circuits connected to the power source.

Circuit for limiting inrush current through a transistor

A redundant power supply with a number of loads is coupled to each half of the redundant supply by a respectively different MOSFET switch, with logic gates coupling control signals to the MOSFET switches. The control signal is coupled as one input to the logic gate and the output of the logic gate is connected to the MOSFET switch. The other input of the logic gates for a particular power supply is the output of an overvoltage detection circuit whose output is coupled as an input to all the gates for that power supply. The output of the gates opens the MOSFET switches in response to detection of an overvoltage condition.

Multi-channel overvoltage protection circuit

A MOSFET switched, redundant power supply has a back-to-back MOSFET switch connecting respectively each power supply to a single load. Each power supply has a positive and negative gate voltage source. In a specific N-channel MOSFET embodiment, the positive (i.e. on) bias is coupled to each switch via a radiation hardened, redundant analogue switch capable of being driven by, for example, a TTL or CMOS microprocessor signal. The negative (i.e. off) bias is coupled to each via a redundant diode pair. In addition, the gates of the back-to-back MOSFET switch for one power source are also connected to the negative bias of the other power source. In this way the MOSFET switch for a failed power supply will be maintained in an off state by the negative bias provided by the redundant supply.

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Centreville, VA, United States of America

Mark J Jones