Lsi Logic Corporation

Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

Mark J Jander

Richard L Solomon

Michael B Anderson

Gregory Arthur Tabor

Bret S Weber

Timothy E Hoglund

Brian A Day

William K Petty

Brad D Besmer

James A Rizzo

Lakshmana M Anupindi

Jason McGinley

Moby J Abraham

Brian G Reise

Kevin Michael Rishavy

Gregory L Huff

Eugene E Freeman

Raymond F Emnett

Edward F Marchand

Jeffrey D Kasyon

R Brian B Skinner

A redundant array of independent drives controller and board controlled cache off-loading during a power failure is described. Methods associated with the use of the redundant array of independent drives controller and board for controlled cache off-loading during a power failure are also described.

Control logic design to support USB cache offload

The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and Ethernet connection which may be used for providing alerts regarding the health of the components of the boot appliance and/or data storage system to a monitoring system, such as a network management system. The boot appliance may provide a boot drive and operating system image to multiple servers at the same time.

Storage system with boot appliance for improving reliability/availability/serviceability in high density server environments

A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Method and apparatus for providing precise circuit delays

A bridge translates addresses between a first bus and a second bus, with a larger address space capability. The bridge stores &ldquo;high address&rdquo; information and combines that information with address information from a device on the first bus when the device desires to transfer information from the first bus to the second bus. The bridge accesses high address information using information identifying the device.

Apparatus and method for address translation in bus bridge devices

A RAID controller integrated into a single chip. The RAID controller chip includes a general purpose RISC processor, memory interface logic, a host CPU PCI bus, at least one back-end I/O interface channel, at least one direct memory access (DMA) channel, and a RAID parity assist (RPA) circuit. The RAID chip enables higher integration of RAID functions within a printed circuit board and in particular enables RAID function integration directly on a personal computer or workstation motherboard. The back-end I/O interface channel is preferably dual SCSI channels. The RAID chip is operable in either of two modes. In a first mode, the chip provides pass through from the host CPU interface directly to the dual SCSI channels. This first mode of operation, a SCSI pass-through mode, allows use of the chip for non-RAID storage applications and enables low level manipulation of the disk array in RAID applications of the chip. The first mode of operation permits use of the chip without change to host applications and drivers. Rather, the chip is operable in a manner compatible with known available SCSI controller devices. The second mode of operation, a RAID control mode, provides full RAID management features to the attached host CPU. In the preferred embodiment, the RAID chip presents an Intelligent I/O (I2O) interface to the host CPU to enhance portability and performance of the host/RAID interaction.

Integrated single chip dual mode raid controller

A first-in-first-out (FIFO) memory system. The FIFO memory system contains a first fall-through FIFO having an input and an output. A pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO is connected to the output of the first fall-through FIFO. The FIFO memory system also includes a second fall-through FIFO having an input and an output, wherein the input of the second fall-through FIFO is connected to the output of the pointer-based FIFO, wherein data placed into the input of the first fall-through FIFO appears at the output of the second fall-through FIFO in a first-in-first-out basis.

N-deep fixed latency fall-through FIFO architecture

A bridge translates addresses between a first bus and a second bus, with a larger address space capability. The bridge stores 'high address' information and combines that information with address information from a device on the first bus when the device desires to transfer information from the first bus to the second bus. The bridge accesses high address information using information identifying the device.

An improved CMOS driver circuit for driving a fast, single-ended, wired-or bus architecture. The driver circuit provides a user-selectable active deassertion assist feature which assists a passive terminator circuit in quickly pulling-up a data or control bus line. The resulting driver circuit provides greater noise immunity to negative voltage transients that result from impedance mismatches caused by poor cable design configurations.

CMOS driver for fast single-ended bus

Growing community of inventors

Colorado Springs, CO, United States of America

Mark J Jander