Zenith Data Systems Corporation

Nec Corporation

Vantus Technologies, Inc.

Vantus Technology

Mark J Foster

Saifuddin T Fakhruddin

Scott A Hovey

James L Walker

Mark A Ruthenbeck

Steven L Belt

Jiming Sun

Brian D Willoughby

Michael D Maddix

Rodman S Brahman

Michael P Krau

Matthew B Mendelow

Randy J VanderHeyden

Babu Rajaram

Saifee Fakruddin

Brian C Barnes

Robert A Kohtz

Lloyd W Gauthier

Anthony M Olson

David J DeLisle

Clark L Buxton

Saifee Fakhruddin

Jeff Schindler

David R Veit

Gregory Allen Mart

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.

Suspend/resume capability for a protected mode microprocesser

Suspend/resume capability for a protected mode microprocessor

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, setup changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.

A computer system has a processing unit with suspend/resume capability, a memory, and a hard disk drive. In response to a first command from the processor, the hard disk drive sends its status to the processor and the processor stores it in the memory. In response to a second command from the processor, the hard disk accepts from the processor the status retrieved by the processor from the memory, and restores itself to this status. In an alternative embodiment, the hard disk drive response to the first command by storing its status on its own hard disk, and responds to the second command by restoring this status from the hard disk. In each case, an output line from the hard disk used to control a light emitting diode is also selectively used to create an interrupt to the processor which facilitates the systems entry into the suspend mode.

Method and apparatus facilitating use of a hard disk drive in a computer

Interrupt for a protected mode microprocessor which facilitates

A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. The system includes a first interrupt mask register having a bit for indicating whether an interrupt is to be recognized by the processor, a second interrupt mask register having a bit for indicating whether the interrupt is to be recognized by a further circuit, and an arrangement responsive to a load of the first mask register for conforming the bit of the second mask register to the bit of the first mask register in a manner invisible to an application program being executed by the processor.

Apparatus for maintaining one interrupt mask register in conformity with

A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.

Personal computer having dedicated processors for peripheral devices

In response to an address decoded in a preselected range, a multiplexer combines translated high order address bits with CPU-generated low order address bits to access random access memory, especially reserved range random access memory. Otherwise, the multiplexer merely combines CPU-generated low order bits with CPU-generated high order address bits to access RAM. An expanded memory specification memory map drives the translator to generate the translated high order address bits. This generates the address for reserved range RAM. RAM contents, normal and reserved range, are available for processing by the CPU.

Method of combining lower order and translated upper order bits to

A method and main memory system that provides a processor cache includes. Dual-port random access memory devices used for main memory, with one port providing typical random access and a second port being associated with an internal shift register that contains sequential instruction words. Improved system speed can be achieved by virtue of the shorter access time of the second port. A preferred embodiment is adapted to employ conventional video random access memory devices as constituents of a main memory system with unique control methods.

High speed memory for microcomputer systems

A computing device includes a system control processor, a built-in keyboard having a plurality of keys, a connector which facilitates connection of an external keyboard or keypad to the device, an electronic switch which is controlled by the internal keyboard processor and can electrically couple the connector to the system control processor. The internal keyboard processor monitors signals from the system control processor, connector and internal keyboard keys in order to open and close the analog switch so as to facilitate transfers between the system control processor and the internal keyboard through itself, and transfers between the system control processor and an external keyboard through the electronic switch.

Method and apparatus facilitating communication between two keyboards

A computer bus interface suited to connecting an expansion bus to a computer's internal bus. The interface is capable of selecting and deselecting any devices coupled to the expansion bus by enabling and disabling buffers which intercept signals between the expansion bus and the internal bus.

External expansion bus interface

A method and apparatus for monitoring the voltage discharge of a battery power supply while under load, and to manage the power supply by accurately calculating the time the useful charge is nearly depleted, providing a series of warnings to the user-operator of that fact, and subsequently performing a system shutdown before a complete discharge of the battery. If the invention is applied to a battery power supply for a computer, the series of warnings enable the computer operator to transfer data from a temporary memory to permanent storage in the time interval between a warning signal and computer shutdown; and since computer shutdown is effected before the battery is fully discharged a battery-destructive phenomenon known as a polarity cell reversal is prevented. The battey monitoring and management techniques disclosed comprise generating periodically at a first rate a voltage-discharge value (SS) indicative of the rate of change of battery discharge voltage with respect to the elapse of time while the battery power supply is under load, generating periodically at the first rate a compensation-factor value (CF) which is numerically larger in absolute value than the absolute value of SS during at least the initial portion of the startup voltage depression and which is thereafter periodically decremented at a second rate until CF reaches a predetermined fixed value (FCF) approaching the SS of the stable section of the voltage discharge curve, and generating periodically at the first rate a real-time compensated voltage-discharge value (CSAV) in accordance with the functional expression: ##EQU1## The real-time CSAV(s) determine the particular battery management step taken.

Method and apparatus for battery-power management using

An improved method for refreshing dynamic random access memory devices is disclosed. Normal refresh clocking signals are monitored and a count accumulated up to a selected value. Refresh operations are then initiated less frequently and only when the selected count has been accumulated. Once control of the bus to the memory has been achieved, a burst of refresh operations are performed prior to release of the bus. Improved efficiency and operating speed may be achieved by minimizing wasted time associated with acquisition and control of the bus. A preferred embodiment illustrates savings associated with a burst of four refresh operations each time the bus to the memory device is acquired for refreshing. Page addressing techniques are enhanced by forcing a change of state of the row address strobe line bus frequently than typical refresh operations.

Growing community of inventors

Lincoln, MI, United States of America

Mark J Foster