Intel Corporation

Mark J Christopherson

Steven E Wells

Robert N Hasbun

Mark E Bauer

Albert Fazio

Kurt B Robinson

Terry L Kendall

Greg Atwood

Phillip M Kwong

A flash EEPROM memory device including a plurality of blocks of flash EEPROM memory cells arranged to be accessed in rows and columns, a query memory storing data defining characteristics of the flash memory device that may be used to initialize software device drivers for accessing the device, and an interface for receiving data and commands addressed to the blocks of flash EEPROM memory cells and generating signals for affecting the purpose of the commands in the flash EEPROM memory device, the interface adapted to receive a command scaled to a range of characteristics of a particular flash EEPROM memory device and respond by returning the data stored in the query memory as output depending on characteristics of the particular flash EEPROM memory device.

Interface for flash EEPROM memory arrays

A method and apparatus for correcting errors in a multilevel cell memory is described. A multilevel cell memory is comprised of multilevel cells, each capable of storing two or more bits of data. A plurality of data bits is received by the multilevel cell memory. The plurality of data bits are sorted into two or more data words. Error correction codes are generated for each of the two or more data words. A memory element bit pattern is formed that comprises one bit from each of the two or more data words. A charge state associated with the memory element bit pattern is stored in one of the multilevel cells.

Method and apparatus for correcting a multilevel cell memory by using

A method of protecting the accuracy of sector of data while the writing the sector of data into a block of a solid state memory disk. First, a sector offset is written into the block to indicate where within the data space of the block the sector data will be located. Second, the sector of data is written into the block. Afterward, the logical sector number that identifies the sector of data is written into the block in two steps. The first step in writing the logical sector number is to write a selected invalid logical sector number into the block. Next, the selected invalid sector number is converted into the valid sector number by programming a power-off bit of the selected invalid logical sector number. Thus, whenever power to the solid state disk is next turned on, the loss of a sector of data and the validity of the sector of data can be determined. The loss of a sector of data is identified by locating a header in the block whose only valid data is the sector offset. The validity of a sector data can be determined by examining the logical sector number. Also described is a method of preventing the introduction of invalid data into the solid state disk as a result of loss of power during the erasure of a block.

Method of detecting loss of power during block erasure and while writing

A method of utilizing circuitry including error detecting and correcting circuitry to detect and correct errors which can occur in data stored in multi-bit per cell format in a flash EEPROM memory array before those errors can affect the accuracy of data provided by a flash EEPROM memory array.

Error management processes for flash EEPROM memory arrays

A memory system contains a plurality of memory cells, a sensing circuit, and a translator circuit. The memory cells store one of a plurality of threshold levels, wherein the threshold levels demarcate windows for designating more than a single bit of data for each memory cell. The sensing circuit, coupled to the memory cells, generates at least one binary coded bit from the threshold level sensed. A translator circuit translates the binary coded bits to gray coded bits such that only one bit changes state between adjacent threshold levels. Because of this, a decrease from one threshold level to a lower adjacent threshold level in a memory cell results in the change of only a single bit of data, thus improving the memory system reliability. The memory system also includes the ability to store threshold states in either a multi-level cell mode or a standard level cell mode. In the standard cell mode, the translator circuit directly passes the binary coded bits without performing any translation.

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Folsom, CA, United States of America

Mark J Christopherson