Motorola Corporation

Texas Instruments Corporation

Freescale Semiconductor,inc.

Mark J Chambers

James B Phillips

Jaime Andres Borras

Jesus S Pena-Finol

Alan I Chaiken

Jesus P Finol

Armando J Gonzalez

Cesar W Carralero

Albert H Higashi

Jesus L Finol

Philippe Gorisse

S Hossein Beladi

Erica G Miller

Sayed H Beladi

Jesus S Finol

Levent Y Erbora

Jose O Perez

Fatima D Da Costa Seidel

A Finite Impulse Response (FIR) filter circuit () includes delay elements (), multipliers (), a summing device (), and a digital integrator () at the output of the FIR filter circuit (). A method for processing data using the FIR filter circuit () includes differentially encoding data prior to storing or processing of the data. The method provides a technique for compressing data since less memory is needed to store derivative data. The method further includes integrating the derivative data using the digital integrator () to decompress the derivative data.

Circuit and method for processing data

A variable gain amplifier to output a differential output signal includes an input circuit to input a differential input signal, a buffer circuit to buffer the differential output signal to a common mode voltage, a compensation circuit to compensate the differential output signal to prevent variation in the differential output signal, and a comparison circuit to compare the common mode voltage to a predetermined voltage and to adjust the common mode voltage to equal the predetermined voltage.

High-speed low-capacitive load common mode feedback

An asymmetry correction circuit for correcting an asymmetry signal includes a first transconductance circuit for transforming the asymmetry signal to a bias current in a first current path, a second transconductance circuit to form the bias current in a second current path, and a feed-forward circuit for transforming the asymmetry signal to a positive difference current and a negative difference current.

High-speed CMOS buffer circuit with programmable quadratic transfer function

A method and apparatus provides control of the gain of an input amplifier (306) in a radio receiver (300), such as in a radiotelephone handset (104). The radio receiver (300) includes an automatic gain control circuit (318). The automatic gain control circuit (318) includes a timer circuit (370) which provides asynchronous, digital automatic gain control circuit to perform a coarse gain adjustment. The automatic gain control circuit (318) further includes an integrator (366) which provides analog automatic gain control for providing remaining needed gain regulation. The automatic gain control circuit (318) provides substantial reduction in input signal acquisition time for the radio receiver (300).

Fast automatic gain control circuit and method for zero intermediate

A transmitter (300) sends a transmitted current (I.sub.203, I.sub.204) along a transmit signal path (203, 204) to a receiver (400) having a low input impedance. The receiver includes a transistor structure (402, 404) that amplifies the transmitted current and feeds it back to the input of the receiver to maintain the low input impedance and a substantially constant voltage on the transmit signal path. The substantially constant voltage at the input of the receiver avoids interference with other circuits (206, 208) located along the transmit signal path.

Current mode transceiver circuit and method

A tuning circuit (202) uses a precision current reference (Iref) along with an analog-to-digital converter (218) to produce a digital output (228) to represent variations of internal resistance values. The precision current reference (Iref) is fed to an internal tuning resistor (R210) in order to provide an analog voltage signal to the analog-to-digital converter (218). The analog voltage signal changes in accordance with the variations in the tuning resistor value over process and temperature. The digital output (228) controls programmable capacitor arrays (C220, C222) which are included in the tuning circuit (202) as well as in an active RC filter (208) whose bandwidth is controlled by the programmable capacitor arrays (C220, C222) and internal resistors (R212, R214, R216).

Tuning circuit for an RC filter

An operational transconductance amplifier (500) includes an input stage (502) having a first and second amplifiers (504, 508) driving class-AB, push-pull amplifiers (506, 510). The input stage (502) receives a differential input signal at first and second amplifier inputs (528, 540). The push-pull amplifiers (506, 510) establish differential currents in a transconductance-setting resistor (512), thereby eliminating the need for static current sources. The biasing levels established by the first and second amplifiers (504, 508) to drive the push-pull amplifiers (506, 510) also control a current source (514). Currents from the current source (514) are summed and provided to amplifier outputs (594, 596).

Low current drain operational transconductance amplifier

A transconductance scaling circuit (500) includes an operational transconductance amplifier (504) having a tunable voltage, V.sub.tune2. A feedback loop controls the tunable voltage, V.sub.tune2, in response to the digital programming of the transconductance amplifier (504) and provides the tunable voltage as a current scaling output.

Transconductance scaling circuit and method responsive to a received

A radio having two architectural platforms integrated in one integrated circuit (IC). A synthesizer controller (312) selects between an offset local oscillator (LO) synthesizer (318) and a second LO synthesizer (316) to provide a common architecture for either an Frequency Division Duplex (FDD) or Time Division Duplex (TDD) system design while providing isolation between the two frequency sources. An offset LO signal (319) is translated to an isolated LO signal 310 and combined with a main LO signal (322) to provide the FDD platform. A second LO signal (314) is translated into the isolated LO signal 310 and combined with the main LO signal (322) to provide the TDD platform. The second LO synthesizer signal (314) is common to both systems in the receive mode.

Radio architecture with dual frequency source selection

A DC translation circuit (200) provides maximum dynamic range in DC level shifting that is temperature and process invariant. The DC translation circuit (200) includes a bandgap reference (202) and current mirror circuit (204) for providing a reference current, Iref. An op-amp circuit (210) receives an AC signal centered about a first DC level, and translates the first DC level into a second DC level using the reference current, a current mirror circuit (208), op-amp circuit (210) and resistor (R2).

DC level shifting circuit for analog circuits

A continuous time common mode feedback amplifier CTCMFB (300) is suitable for applications requiring fully differential amplifiers in low voltage supply requirements. Two mirror image, low gain CMOS amplifiers (MP0/MP2 and MP3/MP4) in the CTCMFB (300) define and stabilize the common mode output voltage, Vcm, of the main differential amplifier (102). The transient response of the common mode amplifier (300) can be adjusted independently of the transient response of the main differential amplifier (102), allowing fast transient response to the main differential amplifier.

Growing community of inventors

Gilbert, AZ, United States of America

Mark J Chambers