Via Technologies, Inc.

Ip-first, LLC

Mark J Brazell

Darius D Gaskins

James R Lundberg

Raymond A Bertram

Vanessa Canac

Matthew Russell Nixon

Alexander Dankwart Essbaum

A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.

Microprocessor with selective substrate biasing for clock-gated functional blocks

A microprocessor including a substrate bias rail providing a bias voltage during a first operating mode, a supply node providing a core voltage, a clamp device coupled between the bias rail and the supply node, and control logic. The control logic turns on the clamp device to clamp the bias rail to the supply node during a second operating mode and turns off the clamp device during the first operating mode. The clamp devices may be implemented with P-channel and N-channel devices. Level shift and buffer circuits may be provided to control the clamp devices based on substrate bias voltage levels. The microprocessor may include a substrate with first and second areas each including separate substrate bias rails. The control logic separately turns on and off clamp devices to selectively clamp the substrate bias rails in the first and second areas based on various power modes.

Microprocessor with substrate bias clamps

A method for placing spare cells into an auto-place-route (APR) block of an integrated circuit is disclosed. The list of functional cells to be included in the block is determined along with the netlist. The sum of the areas of the functional cells and the desired spare cell area is used as the area of the block boundary. The boundary is provided as input to an auto-placement tool along with the netlist and the list of functional cells. The list of functional cells specifically does not include the spare cells so that the tool does not place spare cells in the boundary. Consequently, the spare cell area may be utilized as wiggle-room by the tool to efficiently place the functional cells. The tool produces a placement of the functional cells that includes white space in the boundary. Spare cells are then placed into the white space.

Method for allocating spare cells in auto-place-route blocks

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Cedar Park, TX, United States of America

Mark J Brazell