Intel Corporation

Mark J Balmer

Mark R Waggoner

Steven M Farrer

Ron Whitsel

A method and apparatus for providing programmable self-testing in a memory. Registers in the memory are programmed with a sequence of instructions for performing the self-test of the memory. The sequence of instructions is run to perform the self-test of the memory, and the results are checked. The memory includes a clock multiplier which allows the registers to be programmed at a first clock rate, then the memory is tested at a second clock rate which is faster than the first clock rate.

Programmable built-in self-test function for an integrated circuit

A computer system includes a microprocessor and an external cache memory coupled to the microprocessor. The cache memory includes a memory array and an apparatus for initiating a routine to test the integrity of the memory array in response to a signal asserted by the microprocessor. The apparatus generates a two-bit status signal coupled to the microprocessor for communicating IDLE, ACTIVE, PASS and FAIL states of the test routine. The apparatus initiates the test routine a predetermined of number clock cycles after the assertion of the signal provided by the microprocessor.

Interface protocol for testing of a cache memory

The invention provides a register, which when set to a specific value, ensures that memory accesses take at least a specified number of clock cycles. The invention specifically introduces delays into the memory accesses when a memory bank control register is configured to operate the memory bank in a fast-CAS (fast column address strobe) mode of operation. The delays are introduced transparent to the values in the memory bank control register that otherwise controls the operation of the memory bank. The delay introduced by the invention permits an in-circuit-emulation (ICE) system sufficient time to transfer trace data from the microprocessor to the ICE-base.

Transparently inserting wait states into memory accesses when

A micro processor emulator in which an SMM flag is set whenever a processor being emulated enters system management mode (SMM) mode, a diminished power mode, and is reset when the processor leaves SMM mode. Events, such as branch instructions, that are recorded in a trace memory while the processor is in SMM mode (when the SMM flag is set) are recorded as a trace frame comprised of a trace word and an associated in system management mode (IN.sub.-- SMM) trace bit. When a user evokes interrogation mode of the emulator, the IN.sub.-- SMM trace bit is used to calculate correct physical addresses for disassembly of the recorded trace information.

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Tigard, OR, United States of America

Mark J Balmer