Infineon Technologies Ag

Mark Isler

Christoph Ludwig

Ricardo Pablo Mikalo

Jens-Uwe Sachse

Jan-Malte Schley

Joachim Deppe

Christoph Kleint

Elard Stein Von Kamienski

Günther Wein

Erwin Schroer

Rainer Hagenbeck

A method is provided for operating an electrical writable and erasable memory cell, which has a channel region that can be operated in a first and a second direction, wherein information is stored as the difference of an effective parameter.

Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories

A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.

Charge trapping device and method of producing the charge trapping device

An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.

Charge-trapping memory device

Growing community of inventors

Dresden, Germany

Mark Isler