Infineon Technologies Ag

Qimonda Ag

Mark Hollatz

Peter Lahnor

Klaus-Dieter Morhard

Andreas Roemer

Dirk Többen

Alexander Trüby

Andreas R&ouml;mer

A method is provided for fabricating a semiconductor structure, such as a DRAM memory cell, that includes an elevated region with at least one sidewall. The at least one sidewall is provided with an insulation layer. A mask layer is applied to the insulation layer. The mask layer is patterned in such a way that it is removed from the surface of the elevated region and from an edge region of the insulation layer, said edge region adjoining the sidewall of the elevated region. A material is implanted into the surface of the elevated region and also into the edge region of the insulation layer. The material preferably alters the properties of the surface of the elevated region and also increases the etching rate of the insulation layer. The mask layer is removed and the insulation layer is subjected to a whole-area etching step.

Method for fabricating a semiconductor structure

The invention relates to a method for the planarization of a semiconductor structure comprising a substrate, in which several sub-structures (STI; AA; AA'; AA&#x2033;;) are provided. said sub-structures (STI; AA; AA&#x2032;; AA&#x2033;,) having a first sub-structure (AA&#x2032;) with planar regions (PS) and first trench regions (DT). A layer to be planarized is applied over the semiconductor structure, said layer having appropriate recesses above the first trench regions (DT) of the first sub-structure (AA&#x2032;). The method comprises the following steps: pre-planarization of the layer to be planarized by an etching step, using a pre-planarization mask, then subsequent planarization of the layer to be planarized by a chemical-mechanical polishing step. According to the invention, a first region (B) is formed on the layer to be planarized above the first sub-structure (AA&#x2032;) by means of the pre-planarization mask, said region having a predetermined grid of masked and unmasked sections (M; O) are arranged in such a way that they respectively cover both first trench regions (DT) and planar regions (PS), and a supporting structure for the chemical-mechanical polishing step, which corresponds with the masked sections (M) of the grid, is created by the etching step, using the pre-planarization mask.

Method for the planarization of a semiconductor structure

A process for abrasive machining of surfaces of semiconductor wafers, in particular during the production of electronic memory elements, is described. In the process, a topography of the surfaces of a plurality of wafers is planarized by an at least partially mechanical route. In a further process step which takes place at a later stage, further material is removed from the planarization surfaces by the action of a liquid, chemical composition (etchback). After the planarization step and before the etchback step, a layer thickness measurement of the planarized layer is carried. The method is distinguished by the fact that the measurement results of the layer thickness measurement are used as the basis for the automatic selection or formulation of one of a plurality of chemical compositions and/or the time of action of a selected or formulated chemical composition for carrying out the etchback step.

Process and device for the abrasive machining of surfaces, in particular semiconductor wafers

A process is described for the chemical mechanical machining of semiconductor wafers. A plurality of surfaces are successively subjected to a polishing step, in which they are brought into contact with a polishing device. The polishing device contains a polishing-grain carrier with polishing grains, and the surfaces are moved relative to the polishing device. Material is removed from the surface by the polishing grains, which are fixed in the polishing-grain carrier and may become partially detached from the carrier material during the polishing operation. In each case one or more polishing steps is preceded by a conditioning step for regeneration of the polishing device. The polishing device and a conditioning surface of strong structure are brought into contact with one another and moved relative to one another, with the result that starting states of the polishing-device surface at a beginning of the individual polishing steps are comparable with one another.

Process for the abrasive machining of surfaces, in particular of semiconductor wafers

A substrate holder is described which has a movable plate elastically mounted inside a main body. With the substrate holder, a polishing operation can be performed in two basic operation modes corresponding to two different vertical end positions of the movable plate. In a first (downward) mode the movable plate stays in mechanical contact with the substrate whereas in a second (upward) mode an air cushion is generated in a chamber between the movable plate and the substrate for pressurizing the substrate onto the polishing pad.

Growing community of inventors

Neustadt, Germany

Mark Hollatz