Infineon Technologies Ag

International Business Machines Corporation

Applied Materials, Inc.

Other

Siemens Aktiengesellschaft

United Microelectronics Co.

Infineon Technologies North America Corp.

Mark Hoinkis

Erdem Kaltalioglu

Timothy Joseph Dalton

Kaushik Arun Kumar

Douglas C La Tulipe, Jr

Andy Cowley

Chih-Chao Yang

Lawrence Alfred Clevenger

Andrew Herbert Simon

Steffen K Kaldor

Eric Andrew Joseph

Hiroyuki Miyazoe

Yun-Yu Wang

Jochen Schacht

Roy Charles Iggulden

Chun Yan

Andrew P Cowley

Larry Clevenger

Gerald R Friese

Stefan J Weber

Clement Hsingjen Wann

Soon-Cheon Seo

Terry Allen Spooner

Chandrasekhar Narayan

Kwong Hon Wong

Matthias Hierlemann

Axel Christoph Brintzinger

Florian Schnabel

Stefan Weber

Robert Van Den Berg

Dennis J Warner

Haining S Yang

Michael A Guillorn

Kenneth Parker Rodbell

Herbert Lei Ho

Ronald G Filippi

Hyun K Lee

Hans-Joachim Barth

Stephen Mark Rossnagel

Markus Brink

Nicholas C M Fuller

Darryl D Restaino

John A Miller

Brett H Engel

Sven Schmidbauer

Herbert Palm

Sumit Agarwal

Alexander Ruf

Markus Naujok

Bradley J Howard

Douglas La Tulipe

Steven H Boettcher

Mohammed Fazil Fayaz

Pak Leung

Yi-Hsiung Lin

Michael Stetter

Bang N To

Hans W Poetzlberger

Chiu-Pien Kuo

Ann Chien

Jeffery L Hurd

Ebrahim A Mehter

Matthias P Hierlemann

Erdum Kaltalioglu

Steffen Kaldor

Hyun Koo Lee

Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.

Methods for etching a metal layer to form an interconnection structure for semiconductor applications

Methods of patterning conductive layer with a mask are described. The methods include low-ion-mass sputtering of the conductive layer by accelerating (e.g. helium or hydrogen containing ions) toward a substrate which includes the patterned mask and the underlying conductive layer. The sputtering processes described herein selectively remove conductive layers while retaining mask material.

Selective sputtering for pattern transfer

A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma.

Sputter etch processing for heavy metal patterning in integrated circuits

A method for fabricating a plurality of conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, forming a spacer in a layer of the multi-layer structure residing above the layer of conductive metal, wherein the spacer is formed from a metal-containing atomic layer deposition material, and transferring a pattern from the spacer to the layer of conductive metal using a sidewall image transfer technique, wherein the transferring results in a formation of the plurality of conductive lines in the layer of conductive material.

Sidewall image transfer for heavy metal patterning in integrated circuits

Methods of removing copper residue from interior surfaces of an etch process chamber are described. A plasma treatment using halogen-containing precursors transforms the copper residue into halogen-copper complexes. Plasma-excited inert gases are used to desorb the halogen-copper complexes. In this way, the copper residue is removed from the interior surfaces of the etch process chamber.

Copper residue chamber clean

A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.

Subtractive plasma etching of a blanket layer of metal or metal alloy

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Method and apparatus of stress relief in semiconductor structures

An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Back end interconnect with a shaped interface

A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Bilayered metal hardmasks for use in dual damascene etch schemes

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

Dual damascene structure and method

Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

Reduction of the shear stress in copper via's in organic interlayer dielectric material

Bilayered metal hardmasks for use in Dual Damascene etch schemes

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Fishkill, NY, United States of America

Mark Hoinkis