Storage Technology Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Maxtor Corporation

Exabyte Corporation

Mark Hennecken

Keith Gary Boyer

Steven Gregory Trabert

Robert G Brocko

Michael Lawrence Leonhardt

Richard A Gill

James C Cates

Mark Lee Watson

Matthew P Wojciechowski

Jin Lu

Ronald Dean Gillingham

Edward Virgil Denison

Michael A Blatchley

Larry Blanchard

David J Pereira

A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out ('FIFO') memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory.

Auxiliary path iterative decoding

A magnetic head is provided for reading and writing data on a data storage media. A first writer and a first reader write and read data of a first format. A second reader reads data of a second format having different read channels than the first format. A third reader has a width greater than that of the of the first and second readers, and reads data of a third format wider than that of the first and second formats. A tape drive is disclosed with the magnetic head and control circuitry having read channels for each of the readers. A method for fabricating a magnetic head is disclosed by providing first and second bumps each with a reader and writer of a first format, and a third bump with a reader of a second format and a reader of a third format.

Magnetic head and tape drive for reading multiple data formats

A tape drive for reading both new technology tapes and legacy tapes. The tape drive includes a three bump head with two outer read bumps and an inner write bump. The outer read bumps include readers for reading data from tracks of a first width on a first storage tape while the inner write bump includes writers for writing data in tracks of the first storage tape. Legacy readers are provided in the head to read data from tracks of a second width that is greater than the first track width on a second storage tape. The legacy readers are provided by piggybacking or merged-pole techniques in the inner write bump or are provided in one or both of the outer read bumps. The tape drive includes control circuitry with channels for processing data signals from the narrower readers and channels for processing data signals from the wider legacy readers.

Tape drive with read/write head having legacy read elements and with special-purpose read channels

The present invention combines low density parity checking with parallel equalization channels to enhance data retrieval from tape. Viterbi analysis is done as a precursor to the use of at least one low density parity decoder. A signal decoder may include a plurality of viterbi processors and at least one low density parity check decoder. The decoder may receive a plurality of pulse-shaped signals and produces decoded output signals.

Parallel spectral equalization channels with low density parity check codes

The present invention describes a method and system for adjusting the rate of data transfer between a high-speed multi-channel tape drive and a slower-capability network interface. The present invention allows for selectively enabling/disabling active channels to adjust the data throughput to match the data transfer capabilities of the network interface. Such an adjustment optimizes the rate of data transfer between the system and the tape drive by reducing the amount of stop and start operations normally present in an environment where the network interface cannot support the high-speed data transfer rates of a tape drive. Such an enablement/disablement adjustment system allows for a greater range of varying data rates within the transfer.

Throughput optimization by activation of selected parallel channels in a multichannel tape drive

In a tape drive for storing and retrieving information to and from a media, a system for optimizing write performance includes a tape head and a controller. The tape head may include a write element. The controller may be for optimizing write performance in response to at least one media information signal that is stored on a media cartridge.

System and method for read/write optimization

A method and system are disclosed for providing a variable speed digital read channel. The read channel includes an analog portion and a digital portion. The read channel includes an analog-to-digital converter (ADC) for converting an analog read signal into a sampled read signal. The ADC is synchronized to a sample clock. The sample clock has a variable clock rate. The digital portion includes a digital filter for reducing noise. The digital filter can be implemented as a low pass filter (LPF), a high pass filter (HPF), or a bandpass filter (BPF). The filter receives the sampled read signal from the ADC. The digital filter is synchronized to the sample clock. The digital filter's cutoff frequencies adjust automatically as the variable clock rate is changed, and does not require reprogramming. The digital portion may also include a digital automatic gain control device.

Digital filtering and digital automatic gain control for a variable speed read channel

A tape drive for use with magnetic tapes includes a housing for receiving a magnetic tape having multiple parallel tracks, and a tape head for reading and writing the parallel tracks of the magnetic tape. A plurality of partial response maximum likelihood (PRML) equalization/detection channels are provided for processing the data signals to determine the data stream for each data signal. The plurality of PRML equalization/detection channels includes at least one PRML equalization/detection channel pre-assigned to each track. The plurality of PRML equalization/detection channels further includes at least one floating PRML equalization/detection channel dynamically assignable on an as-needed basis. The invention also contemplates an ASIC, a generic drive, and a PRML method.

Dynamically allocated parallel equalization and detection of a PRML read channel in a multi-channel drive

A system and method for decoding magnetic media. Parallel decoders, each with a different equalization magnitude, are used to decode a read signal. A Viterbi metric is used to determine the direction and magnitude of equalization shift that best compensates for a systematic separation, such as pole tip recession. If optimal equalization has changed, the equalization coefficients of the decoders is shifted to compensate.

Read equalizer optimization based on the PTR effects to write equalization

A method and apparatus for allowing communication between a stationary circuit and circuitry in motion with respect to the stationary circuit is presented. Communication is achieved and verified by transmitting a clock signal and a control signal in synchronization with the clock signal over separate clock and control transformer channels between the stationary circuit and the moving circuitry.

Drum electronics control interface and protocol for recording/reproducing apparatus

A servo track write head writes low frequency transitions for fine transverse positioning and high frequency fields providing additional information. The servo track write head includes a first write gap with at least one gap section at a first angle relative to a tape direction. A second write gap has at least one gap section at a second angle, not equal to the first angle. The first and second write gaps write low frequency transitions in each servo frame. A third write gap writes high frequency transitions in each servo frame.

Servo write head with gaps for writing high and low frequency transitions

Servo tracks combine low frequency transitions for fine transverse positioning with high frequency fields providing additional information. In one embodiment, each servo frame has a first field of recorded low frequency transitions, a second field of recorded low frequency transitions, and at least one high frequency field. The first low frequency field transitions are recorded on the tape such that a peak of each first field transitions varies in longitudinal position across the width of the servo frame. The second field of low frequency transitions are recorded on the tape such that a peak of each second field transition is not parallel with the peak of any first field transition. High frequency fields may provide one or more of timing information, longitudinal position information and gross transverse position information.

High frequency and low frequency servo pattern

An electronic system for detecting flaws in the magnetic media of raw disks prior to assembly into disk drives which works in conjunction with an electro-mechanical apparatus that performs the functions of spinning the disk, impressing a sinusoidal signal onto the media of the spinning disk and subsequently reading back the signal from the spinning disk. The signal read from the disk is supplied as the electrical output of the electro-mechanical apparatus. The system includes a divider circuit to divide the read signal into two signal channels. An op amp based impedance matching circuit is connected to the output of the dividing circuit in each channel and matches the electrical impedance of the electro-mechanical apparatus with the impedance of the remainder of the electronic detection system. It passes the two signals through substantially unaltered. A two stage op amp based phase shifter circuit is connected to each of the impedance matching circuits and generates two output signals having substantially the same amplitude as the two input signals, but a phase difference with respect to each other of substantially 90.degree. over a frequency range of approximately 3 to 22 megahertz. A multiplier circuit is connected to each phase shifter circuit. These circuits square each of the two output signals from the phase shifting circuits. A summing circuit sums the two output signals from the two multiplier circuits. This produces a DC signal value which is low pass filtered with a large time constant filter. The voltage value of the DC signal is used to determine the reference of a comparator circuit. The comparator circuit compares the amplitude of the output signal of the summing circuit with upper and lower limit values based on the reference and each time the output signal of the comparator circuit exceeds either the upper or lower limit, the comparator supplies an output signal to a computer which keeps track of the defects so determined.

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Parker, CO, United States of America

Mark Hennecken