Apple Inc.

Broadcom Corporation

Google Inc.

P.a. Semi, Inc.

Mark Hayter

Dominic Go

Ruchi Wadhawan

Zongjian Chen

Joseph Byron Rowlands

James Y Cho

Puneet Kumar

Kwong-Tak Chui

James B Keller

Choon Ping Chng

Shailendra S Desai

Josh P De Cesare

Weichun Ku

Chun Hung Ning

Christopher Thomas Lyon

Erik P Machnicki

Linus M Upson

Andrew Bowers

James Tanner

Daniel W Dobberpuhl

Joseph Edward Clayton

David Ness Schneider

Rachel Nancollas

James Han Wang

Michael J Smith

Scott David Johnson

Timothy Jay Chen

Honggang Sheng

Dominic Rizzo

Alec Berg

Olof Johansson

Scott D Redman

Willis Calkins

Eunchan Kim

Frank Hislop

Michael Stefano Fritz Schaffner

Duncan Laurie

Shun Wai Go

Amy K Silveria

An IC chip can provide silicon root of trust (RoT) functionality. In described implementations, the IC chip includes a processor, an interconnect, and multiple peripheral devices. These comportable circuit components are designed to facilitate interoperability and consistent, expected communications for security circuitry. Each peripheral device includes an interface that adheres to a common framework for interacting with the processor and with other peripheral devices. The interface includes an interconnect interface coupling the peripheral device to the interconnect and an inter-device interface coupling the peripheral device to at least one other peripheral device. The peripheral device is realized based on a peripheral device design code that indicates inter-device signaling in accordance with an inter-device scheme of an interface specification. Manufacturers fabricate the peripheral device, based on the design code, to be physically and logically coupled to another peripheral device in a predictable manner. This fosters more-robust and reliable security circuitry.

Peripheral device comportability with security circuitry

A computing system is configured to securely boot different operating systems. The computing system includes one or more processors, a first memory device storing a first firmware element for booting a first operating system, a second memory device storing a second firmware element for booting a second operating system, a first security module configured to provide authentication for booting the first operating system, and a second security module configured to provide authentication for booting the second operating system. The computing system is configured such that, when the first security module is connected to the one or more processors, either the first operating system or the second operating system is selected for booting based on a selection signal, and when the first security module is not connected to the one or more processors, the second operating system is selected for booting.

Enabling multiple secure boot paths on a hardware platform

In one general aspect, a method can include configuring a first connector of a particular type included in a first multipurpose port located on a first side of a computing device to connect the computing device to a first peripheral device, transporting one or more of power, high-speed data, and display data between the computing device and the first peripheral device using the first multipurpose port, configuring a second connector of the particular type included in a second multipurpose port located on a second side of the computing device to connect the computing device to a second peripheral device, and transporting one or more of power, high-speed data, and display data between the computing device and the second peripheral device using the second multipurpose port.

Multi-function ports on a computing device

In one general aspect, a method can include determining an orientation of a plug inserted into a connector included in the computing device, providing a plurality of display data signals to a reordering switch included in the computing device, selecting, by the reordering switch and based on the determined orientation of the plug, a display data signal from the plurality of display data signals, providing the selected display data signal to at least one of a plurality of multiplexers, the plurality of multiplexers being orientated back-to-back, providing a data signal to the at least one of the plurality of multiplexers, enabling the at least one of the plurality of multiplexers, selecting the display data signal for output by the at least one of the plurality of multiplexers, and providing the selected display data signal to a contact included on the connector.

A power brick includes a power module configured to convert AC to DC, an interface coupled to a computing device and configured to communicate with the computing device, and a controller. The controller is configured to receive a modified power setting and at least one modified error threshold value via the interface, control a modification of a power setting associated with the power module, and control a modification of a protection value of the power brick based on the at least one modified error threshold value.

Power adapter charging modification based on a feedback loop

In one general aspect, a method can include obtaining, by a computing device, a lid accelerometer vector for a lid accelerometer included in a lid portion of the computing device, and obtaining, by the computing device, a base accelerometer vector for a base accelerometer included in a base portion of the computing device. The method can include calculating a value for a lid angle based on the lid accelerometer vector and the base accelerometer vector, and identifying an operating mode for the computing device based on the calculated value of the lid angle, the operating mode being one of a laptop mode and a tablet mode.

Detecting an operating mode of a computing device using accelerometers

In one general aspect, a method can include receiving, by a computing device, an indication of movement of the computing device, receiving, by the computing device, an input from one of a touchpad, a touch-sensitive surface of a lid portion of the computing device, a trackpad, one or more mouse buttons, and a keyboard during the movement of the computing device, determining, based on the received indication of the movement of the computing device, that the received input is a false input, and ignoring, by the computing device, the received input based on determining that the received input is a false input.

Selective override of touch display inputs

In a general aspect, a circuit can include a printed circuit board having an opening defined therein and an electrical write line disposed on the circuit board. The electrical write line can be connected to a semiconductor memory device, and be configured to transmit a write voltage signal to the semiconductor memory device to write data therein in a write mode of the circuit. The circuit can also include an input voltage terminal disposed on the circuit board. The input voltage terminal can be configured to receive a write-protection voltage. The circuit can also include a reversible closing element that, when inserted in the opening in the circuit board, electrically connects the electrical write line and the input voltage terminal to pass the write- protection voltage to the electrical write line connected to the semiconductor memory device to reversibly enable a write-protect mode of the circuit.

Methods and apparatus related to a write protect fastener

An apparatus may include a housing, an electronic display region, and a controller. The electronic display region may be coupled to the housing, and may have a rectangular shape with a length and a width, the length being approximately a square root of two (&#x221a;2) times longer than the width. In response to an indication that the housing and the display region have been rotated from the portrait mode to a landscape mode, the controller may be configured to display a first image and a second image, the first image having an aspect ratio defined by a second length of the first image divided by a second width of the first image, wherein the second length is different from the first length, the second width is different from the first width, the second aspect ratio is substantially equal to the first aspect ratio, and the first image being rotated by ninety degrees (90&#xb0;) from the first orientation with respect to the axis.

Display with square root of two aspect ratio

In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Interrupt distribution scheme

In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Data transformation during direct memory access

In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Network direct memory access

Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements

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Menlo Park, CA, United States of America

Mark Hayter