International Business Machines Corporation

Mark Harrison McLeod

Jae-Woong Nah

Claudius Feger

Peter Alfred Gruber

Eric D Perfecto

Sudipta Kumar Ray

Mario John Interrante

Harsaran S Bhatia

Shashi D Malaviya

Herbert I Stoller

Suresh D Kadakia

Joseph L Horvath

Carl Yakubowski

A photoresist layer is applied over a solder resist layer on a substrate such as a wafer. Openings in the solder resist and photoresist layers are filled with flux-free molten solder using IMS. The process is applicable to fine pitch applications and chip size packaging substrates. A protection layer may be employed to facilitate removal of the photoresist layer from the substrate. An oversized substrate including an adhesive layer on a peripheral area may be employed for providing greater adhesion of a dry film layer to the peripheral area of the substrate than the central portion thereof. The peripheral area is removed following IMS.

IMS (injection molded solder) with two resist layers forming solder bumps on substrates

A process and tools for forming spherical metal balls is described incorporating molds, injection molded solder, a liquid or gaseous environment to reduce or remove metal oxides and an unconstrained reflow of metal in a heated liquid or gas and solidification of molten metal in a cooler liquid or gas.

Forming constant diameter spherical metal balls

Solder bumps of uniform height are provided on a substrate through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned layer of photoresist. Solder is injected over the pillars or BLM, filling the channels. The solder, which does not contain flux, is allowed to solidify. It forms a plurality of solder structures (bumps) of equal heights. Solder injection and solidification are preferably carried out in a nitrogen environment or a forming gas environment. Molten solder can be injected in channels formed in round wafers without spillage using a carrier assembly that accommodates such wafers and a fill head.

Injection molded solder process for forming solder bumps on substrates

A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

Direct distribution repair and engineering change system

In an electronic package, improved disk shaped thermal bridge elements provide multiple conductive paths between devices to be cooled and a cold plate. The thermal bridge elements are disks progressively stacked and having bulge shapes and radial finger contacts for providing multiple compliant heat conduction paths between each device and a cold plate.

Multiple radial finger contact cooling device

A test circuit that is particularly suitable for inclusion on an LSI chip when testing a new technology or process. The circuit will enable accurate determination of the effects of loading on the turn-on and turn-off delays of one or more logic circuits on the chip. These determinations are based upon a comparison of the periods of different signals obtainable from the test circuit.

Test circuit for turn-on and turn-off delay measurements

A test circuit that is particularly suitable for inclusion on an LSI chip when testing a new technology. The circuit will enable accurate determination of the turn-on and turn-off delays of a logic circuit on the chip. Two related feedback loops are provided, one of the loops containing the circuit being tested. The differences in time duration between related portions of the two loops correspond to the turn-on and turn-off delays of the circuit being tested.

Growing community of inventors

Poughkeepsie, NY, United States of America

Mark Harrison McLeod