Apple Inc.

Motorola Corporation

Mark H Nodine

Irfan Waheed

Raymond Cheung Yeung

Adrian J Isles

Nathan Francis Sheeley

Warren D Grobman

Harold M Martin

Nicolas Xavier Pena

Anhtu Nguyen

Patrick Peters

This invention () described a method that generates and uses a test bench for verifying an electrical design module in a semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing () a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing () a description of an electrical reference model. The invention further includes providing and or creating () one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing () a description file that includes one or more instance definitions. The invention parses () the hierarchy of the electrical design model and then processes () the description file. The invention then writes () the test bench.

Generating test benches for pre-silicon validation of retimed complex IC designs against a reference design

This disclosure describes a method for accomplishing sequential logical equivalence verification using a hierarchical piecewise approach. Initially, the method provides a reference semiconductor design and a second semiconductor design with logic edits relative to it. The method submits both to formal verification to check the reference design against the second semiconductor design with all edits disabled. The semiconductor design is partitionedand associated input constraints. The edits are further groupedand ordered. The invention also discovers a set of dependencies of the logic editsand checks that the ordering of groups obeys the dependencies. Each group of edits is further submitted to formal verificationand any input constraints assumed for any partitions are verified in their enclosing partition. Finally, the method reports success if formal verification succeeds on each group of logic edits and on each set of input constraints

Method for piecewise hierarchical sequential verification

This disclosure describes a method illustrated in FIG.to prepare re-architected digital logic designs for sequential equivalence checking. This method initially begins with a description of an electrical design module that includes a plurality of ports, and a description of an electrical reference model that comprises a hierarchy of one or more reference modules where each said reference module comprises a plurality of internal signals. In addition, this method includes a configuration file with additional initial information. The method then processesa configuration file. Then, the methodcomputes one or more output files. Finally, the methodwrites the output files.

Method for preparing re-architected designs for sequential equivalence checking

A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity.

Method for preparing for and formally verifying a modified integrated circuit design

This invention () describes a method that generates and uses a test bench for verifying an electrical design module in semiconductor manufacturing against an electrical reference model containing a sub-circuit that matches the electrical design module. The invention includes providing () a description of an electrical design module that includes a plurality of ports. In addition, the invention includes providing () a description of an electrical reference model. The invention further includes providing and or creating () one or more implicit defines for the reference modules that appear in hierarchy of the electrical reference model. And, the invention includes providing () a description file that includes one or more instance definitions. The invention parses () the hierarchy of the electrical design model and then processes () the description file. The invention then writes () the test bench.

Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.

Circuit design verification tool and method therefor using maxwell's

A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated from protocol templates. The correctness evaluator operates according to a 'clean bus' theory that an error includes those events not specified by the circuit specification, including spurious transitions. Protocol templates define the elements within the circuit, and are provided to a prediction generator which creates a prediction file. The correctness evaluator compares a simulation monitor file to the prediction file, and outputs a pass or fail result. The present invention offers a flexible method to separate protocol-defined timing constraints from implementation-dependent timing constraints. The present invention allows input from a test program to tailor bus signal change predictions and verify that the test program performs as it is programmed to perform.

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Austin, TX, United States of America

Mark H Nodine