Motorola Corporation

Mark H Babcock

Mark L Oliboni

David Jeffery Hayes

James A Lamb

Ronald Hugh Evoy

Tuan S Hoang

Carol A McKinny

Annie Yalay Wang

Mark R Whitaker

Christopher B Rausch

A method (600) that adjusts, at a predetermined boundary of a protocol utilized in decoding information from a signal received by a receiver (122), a symbol rate of the protocol (400). A processor (208) loads into a programmable counter (306), before a first boundary (412) of the protocol (400), a count of clock cycles defined to be received in the signal between the first and predetermined boundaries (414). The counter (306) counts from the first boundary (412), for a number of clock cycles equal to the count, a recovered bit clock synchronized with the signal and having the bit rate of the signal, to detect an occurrence of the predetermined boundary (414). The processor (208) loads, between the first (412) and predetermined boundaries (414), the another symbol rate into a bit-rate selection circuit (304). An output symbol rate of the bit-rate selection circuit (304) is enabled upon detecting the occurrence of the predetermined boundary (414), thereby adjusting the output symbol rate to the other symbol rate at the predetermined boundary (414).

Method and apparatus in a communication receiver for adjusting an

A method and apparatus (400) manages a current data symbol received by a receiver (122) in a frame of data of a time diversity communication system (102, 104). A symbol counter (402) counts a signal (404) from a symbol clock synchronized to the frame of data to provide a count of the current data symbol, and a bit line translator (416) maps a current address from the count. A conditional processor (434) derives a selected memory address from the current address. Then, based upon the current address, a comparator (424) makes a choice among (a) storing the current data symbol in a memory at the selected memory address, (b) merging the current data symbol with an earlier received data symbol stored at the selected memory address during an earlier frame of data, and (c) ignoring the current data symbol.

Method and apparatus for managing a data symbol received in a time

A peak and valley detection system and method are shown for a selective call receiving device (10). The peak and valley detection system quickly and accurately detects and tracks to the peak and valley of a two level and/or four-level signal. A signal value representing a received signal is compared by a CPU (28) to the sum of a peak variable and attack constant. The peak variable is updated to a first value if the received signal value is less than the sum and is updated to a second value if the received signal value is not less than the sum. Similarly, the received signal is compared by the CPU (28) to a difference between a valley variable and attack constant. The valley variable is updated to a third value if the received signal value is greater than the difference value and updated to a fourth value if the received signal value is not greater than the difference value. The peak and valley variables attack and decay at non-constant rates and independently of one another.

Peak and valley detector for a selective call receiving device

A logic circuit (260) includes recursive elements (470, 1070, 1400, 1600) interconnected in a matrix (300), and M data inputs (490), and a logic circuit output (475). In one embodiment, N+1 binary column setup inputs (485), and M-N binary row setup inputs (480) are also included. The matrix (300) is an arrangement of the recursive elements (470) in rows, columns, and diagonals. The M data inputs (490) are for coupling the M bits of the binary word to the recursive elements (470). The logic circuit output (475) includes an output (810) of one of the recursive elements (470, 1070, 1400, 1600). The logic circuit output (475) has a binary value determined by a comparison of the number of bits having a first binary value within the binary word, to the predetermined number, N. In the one embodiment, the comparison is determined by the values of the setup inputs (480), (485).

Apparatus for comparing the weight of a binary word to a number

Circuitry for converting analog signal voltages to digital values comprises an analog-to-digital (A/D) converter (170) for receiving an analog signal voltage and analog reference voltages and for generating in accordance therewith a first digital value. The circuitry further comprises first and second digital-to-analog (D/A) converters (175, 180) coupled to the A/D converter (170) for providing the analog reference voltages to the A/D converter (170). A controller (120) coupled to the first and second D/A converters (175, 180) and the A/D converter (170) receives the first digital value and generates therefrom at least a second digital value for subsequent transmission to at least one of the first and second D/A converters (175 or 180), in response to which the at least one of the first and second D/A converters (175 or 180) adjusts at least one of the analog reference voltages provided to the A/D converter (170).

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Austin, TX, United States of America

Mark H Babcock