Semiconductor Components Industries, LLC

Mark Griswold

Weize Chen

Arash Elhami Khorasani

Michael John Seddon

Jaroslav Pjencak

Ali Salih

Mohammed Tanvir Quddus

Johan Camiel Julia Janssens

Mihir Mudholkar

Moshe Agam

Yupeng Chen

Ralph N Wall

Thierry Yao

Derrick Johnson

Sameer S Haddad

Richard David Taylor

Amit Paul

David T Price

Bruce Greenwood

Radim Mlcousek

Kenneth Andrew Bates

Martin Kejhar

Kevin Alexander Stewart

In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

Semiconductor devices and methods of manufacturing semiconductor devices

Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

SOI substrate and related methods

In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

Semiconductor device having a resistor and structure therefor

In one embodiment, a transistor has a drift region that is formed to have a plurality of zones having different vertical doping profiles across the zones. At least one of the zones has a vertical doping profile that has a first peak near a top surface of the zone and a second peak near a bottom surface. An embodiment may have a lower doping in a region that is between the two peaks.

Semiconductor device

An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Process of forming an electronic device including a non-volatile memory cell

In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.

Method of forming a semiconductor device

An electronic device can include a JFET that can include a drain contact region, a channel region spaced apart from the drain contact region, and a gate region adjacent the channel region. In an embodiment, the gate region includes a relatively heavier doped portion and a relatively lighter portion closer to the drain contact region. In another embodiment, a gate field electrode can be extended beyond a field isolation structure and overlie a channel of the JFET. In a further embodiment, a region having relatively low dopant concentration can be along the drain side of the conduction path, where the region is between two other more heavily doped regions. In another embodiment, alternating conducting channel and gate regions can be used to allow lateral and vertical pinching off of the conducting channel regions.

Electronic device including a junction field-effect transistor

Silicon-on-insulator (SOI) substrate and related methods

In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed as an elongated element that is formed into a pattern of a spiral. An embodiment of the pattern of the resistor includes a plurality of revolutions from the starting point to an ending point. The resistor material has one of a separation distance between adjacent revolutions that increases with distance along a periphery of the resistor material or a width of the resistor material that increases with distance along the periphery of the resistor material.

Method of forming a semiconductor device and structure therefor

Method of forming a semiconductor device having a resistor and structure therefor

In a general aspect, an integrated circuit (IC) can include a low-voltage region including a low-side driver circuit configured to control a low-side switch of a power converter. The IC can also include a high-voltage region including a floating region of a first conductivity and a high-voltage sensing device disposed in the floating region. The high-voltage sensing device can include a junction-field effect transistor (JFET), and a voltage divider. The voltage divider can include a first terminal coupled to a drain of the JFET, a second terminal coupled to a gate of the JFET, and a sense terminal, the voltage divider being configured to a provide, on the sense terminal. The IC can further include a high-side driver circuit coupled with the sense terminal. The high-side driver circuit can be configured to control a high-side switch of the power converter based on the voltage on the sense terminal.

Growing community of inventors

Gilbert, AZ, United States of America

Mark Griswold