Hewlett-packard Development Company, L.P.

Hewlett Packard Enterprise Development LP

Mark Gravel

Daniel Joseph Dove

Alan R Albrecht

Paul Allen Bottorff

Steven Glen Jorgensen

Joseph A Curcio

King Wayne Luk

Keng Hua Chuang

Mehrnaz Sharifian

Yee Hong Tan

Lawrence Lee Chee How

Joseph A Curclo, Jr

A cost effective congestion isolation for lossless Ethernet utilizing random selection is provided. Upon detecting congestion at one of its egress ports, a downstream device randomly selects a data packet received at one or more of its ingress ports for isolation in a congested priority queue at the ingress port. The downstream device sends a congestion isolation message, including a list of isolation hashes to an upstream device to identify data packets selected for isolation. Upon receipt, the upstream device identifies data packets selected for isolation and begins to queue such packets in a congested priority queue of the upstream device. When priority-based flow control is triggered, the upstream device ceases transmission of packets in the congested priority queue only, while allowing continued transmission of non-isolated data packets.

Cost effective congestion isolation for lossless ethernet

Systems and methods are provided for fast cyclic redundancy check code generation. For example, a method includes representing the sequence of bits as a polynomial over a Galois field base 2; partitioning the polynomial into a plurality of partial polynomials, wherein the polynomial equals the sum of the partial polynomials; concurrently generating a respective partial CRC code for each of the partial polynomials; weighting each partial CRC code according to a position of the respective partial polynomial in the polynomial; and summing the weighted partial CRC codes.

Fast cyclic redundancy check code generation

Example implementations relate to a bridge port extender. For example, a bridge port extender may include a processor. The processor may receive an Ethernet frame from a network bridge, where the Ethernet frame includes an encapsulated portion and an unencapsulated portion, and where the unencapsulated portion includes an E-tag. The processor may remove the E-tag from the unencapsulated portion to form a modified Ethernet frame. The processor may transmit the modified Ethernet frame to a client device based on the E-tag.

Bridge port extender

A forward counter block may include at least one of a plurality of local counter storage elements for counting events. The forward counter block may also include an update engine, the update engine configured to update an external memory by forwarding a value stored in any of said at lease one of a plurality of local counter storage elements and return a zero value to that local counter storage element, when the value stored in that local counter storage element reaches or surpasses a threshold value.

Forward counter block

A network event indicator system and corresponding method are described. The system includes an event rate classifier and an indicator drive state machine. The event rate classifier receives an event signal representing timing of a network event during a predetermined sample period and transmits an event rate signal. The indicator drive state machine receives the event rate signal and generates a drive indicator signal based on the received event rate signal.

Network event indicator system

A method performed by a networked device for energy efficient operation of an optical transceiver of the networked device is described herein. It is determined whether a port control of the networked device is enabled to operate in an energy efficient state. Where the port control is enabled to operate in the energy efficient state and an absence of a valid receive energy from a link partner is determined, a laser transmitter of the optical transceiver is pulsed by asserting and de-asserting a control signal.

Method for energy efficient pulsing operation of transceivers of a networked device

A plurality of media access controllers (MACs) are time division multiplexed with one or more serializer/deserializer (SerDes) devices, wherein there are more MACs than SerDes devices and/or a single multi-rate Ethernet MAC is able to communicate with a multi-rate PHY spanning speeds from 10 megabits per second to 10 gigabits per second using the same framing mechanism and structure.

Highly flexible and efficient MAC to PHY interface

One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

Growing community of inventors

Roseville, CA, United States of America

Mark Gravel