USA As Represented by Secretary of the Navy

University of California

Rayton Solar Inc.

Northrop Grumman Systems Corporation

Mark Goorsky

Karl D Hobart

Marko J Tadjer

Samuel Graham, Jr

Travis J Anderson

Andrew D Koehler

Tatyana I Feygelson

Michael Anthony Mastro

James Rosenzweig

Andrew X Yakub

Zhe Cheng

Luke Yates

Tingyu Bai

Yekan Wang

Asif Khan

Vincent Gambin

Joshua D Caldwell

Ioulia Smorchkova

Bradford B Pate

Gregory Todd Lewis

Rajinder S Sandhu

Jeff McKay

Monali B Joshi

Eugene I Imhoff

Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InAlN), InGaN, AlGaN, InAlGaN, where (0<x≤1, 0<y≤1, 0<x+y≤1).

Polarization-engineered heterogeneous semiconductor heterostructures

A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred &#x3c;110&#x3e; orientation texture, which in turn enhances the thermal conductivity of the diamond film.

Diamond on nanopatterned substrate

The process for manufacturing a silicon wafer includes steps for mounting a float zone silicon work piece for exfoliation, energizing a microwave device for generating an energized beam sufficient for penetrating an outer surface layer of the float zone silicon work piece, exfoliating the outer surface layer of the float zone silicon work piece with the energized beam, and removing the exfoliated outer surface layer from the float zone silicon work piece as the silicon wafer having a thickness less than 100 micrometers.

Float zone silicon wafer manufacturing system and related process

A method for fabricating a semiconductor device, such as a GaN high electron mobility transistor (HEMT) device, including etching a thermal via into a back-side of a semiconductor substrate and depositing a diamond nucleation seed layer across the back-side of the substrate. The method further includes coating the diamond nucleation with a mask layer and removing mask material outside of the thermal via on the planar portions of the back-side of the substrate. The method includes removing portions of the diamond nucleation layer on the planar portions and then removing the remaining portion of the mask material in the thermal via. The method then includes depositing a bulk diamond layer within the thermal via on the remaining portion of the diamond nucleation layer so that diamond only grows in the thermal via and not on the planar portions of the substrate.

Selective deposition of diamond in thermal vias

Described herein are composite semiconductor substrates for use in semiconductor device fabrication and related devices and methods. In one embodiment, a composite substrate includes: (1) a bulk silicon layer; (2) a porous silicon layer adjacent to the bulk silicon layer, wherein the porous silicon layer has a Young's modulus value that is no greater than 110.5 GPa; (3) an epitaxial template layer, wherein the epitaxial template layer has a root-mean-square surface roughness value in the range of 0.2 nm to 1 nm; and (4) a set of silicon nitride layers disposed between the porous silicon layer and the epitaxial template layer.

Composite semiconductor substrates for thin-film device layer transfer

Growing community of inventors

Valencia, CA, United States of America

Mark Goorsky