Arm Limited

Mark Gerald LaVine

Simon John Craske

Ashok Kumar Tummala

Alan Jeremy Becker

Apurva Patel

Ranjini Mysore Nagaraju

A mechanism is provided efficient packing of network flits in a data processing network. Transaction messages for transmission across a communication link of a data processing network are analyzed to determine a group of transaction messages to be passed to a packing logic block for increased packing efficiency. The transaction messages are packed into slots of one or more network flits and transmitted across a communication link. The mechanism reduces the number of unused slots in a transmitted network.

Method and apparatus for efficient packing of flow control units

Apparatuses and methods for extracting ordered data sub-components from a data item are disclosed. A received data item has a data structure to accommodate multiple data sub-components. The data item indicates which data sub-components are valid. Adders sum respective subsets of indications of the valid data sub-component positions, with each adder covering one more position than the previous adder. Transitions of the counts generated by the respective adders are used to determine the ordinal valid data sub-component positions in the data item, which can then be output on the basis of the data item and the identified transition positions. Without requiring feedback paths from an identified earlier ordinal position to identify a later ordinal position, the set of ordered data sub-components can be extracted more quickly.

Ordered data sub-component extraction

A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

Error correcting bits

An apparatus is provided, which includes monitor circuitry for monitoring the behaviour of processing circuitry and for generating at least a packet indicating the behaviour. Compare circuitry compares the packet to a base packet and generates a delta packet based on the comparison. Compress circuitry forms a compressed packet on the basis of the delta packet. Output circuitry outputs the compressed packet and update circuitry updates the base packet in dependence on one or more triggers.

Packet compression

A data processing apparatus comprises at least one memory configured to store data; processing circuitry to access data in the at least one memory. Memory built-in self-test (MBIST) circuitry has an interface to access the at least one memory and is configured to perform a test procedure for testing at least one target memory location of the at least one memory. The test procedure involves at least writing test data to the target memory location. Diagnostic circuitry executes a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing circuitry. The MBIST circuitry is configured to control writing of the diagnostic data generated by the diagnostic circuitry to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory.

Data processing

Apparatus comprising logic analyzer circuitry comprises a succession of two or more successive trigger condition detectors each configured to detect a match between a respective trigger condition and data handling activity relating to data handling transactions each having a respective transaction identifier; the succession of trigger condition detectors being configured so that a detection by a trigger condition detector of a match with its respective trigger condition enables a next trigger condition detector in the succession to initiate detection of a match with the respective trigger condition of that next trigger condition detector; and a transaction identifier detector associated with a first trigger condition detector in the succession, configured to detect the transaction identifier relating to a data handling transaction for which a match is detected by the first trigger condition detector, and to supply the detected transaction identifier to a subsequent trigger condition detector in the succession of trigger condition detectors; in which the subsequent trigger condition detector is configured to apply the detected transaction identifier as at least a part of its respective trigger condition so as to detect a match only in respect of a data handling transaction having that transaction identifier.

Apparatus and methods for logic analysis to detect trigger conditions relating to data handling transactions in systems using transaction identifiers

A logic analyzeris provided with a state controllerand analyzer circuitry. The logic analyzer switches between a programmable sequence of trigger states and generates an index signal within each trigger state. The index signal is used to control the analyzer circuitry to select appropriate portions of programmable trigger state data so as to configure the matching operation performed against hardware signal values taken from hardware circuitrywhich is subject to analysis by the logic analyzer

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Austin, TX, United States of America

Mark Gerald LaVine