International Business Machines Corporation

Mark G Veldhuizen

Joseph Allen Kirscht

Anthony Gus Aipperspach

Scott Douglas Clark

Kent Harold Haselhorst

Paul William Rudrud

Kerry Christopher Imming

Matthew Roger Ellavsky

Morgan D Davis

Randall Scott Jensen

A method and elastic buffer circuit are provided for implementing low power, single master-slave elastic buffers in a network chip design to provide a continuous stream of data to multiple sinks from multiple sources, and a design structure on which the subject circuit resides. An elastic buffer only uses a single master-slave register. The circuit includes a finite state machine, and a latch control block (LCB) to implement the single master-slave elastic buffer removing all &#xbd; cycle paths between buffer locations enabling usage of the single master-slave register.

Implementing low power, single master-slave elastic buffer

A memory arrangement, where a memory control logic, which drives a memory array, is maintained in a volatile power domain, and clock redrive circuitry, address control redrive circuitry, data transceiver, and the memory array itself are all maintained in a non-volatile power domain, in order to increase the effective life time of a battery backup system. The memory arrangement includes buffering circuitry to prevent leakage currents, and the appropriate control of nets between the memory control logic and the memory array, in order to avoid additional sources of leakage current and bus driver contentions.

Continuously powered mainstore for large memory subsystems

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Rochester, MN, United States of America

Mark G Veldhuizen