Motorola Corporation

Mark G Spiotta

James K Gehrke

Juan C Santiago

Jan P Vanderspool, Ii

Timothy J Groch

Steven P Shipton

Erling Bjerga

John P Foley

An unsynchronized base site (,) transmits a time synchronization request to a communication unit (,). A time synchronization error, or a timing offset, for the unsynchronized base site (,) is then determined and transmitted back to the unsynchronized base site (,) to enable the unsynchronized base site to synchronize itself. The time synchronization error is determined for the unsynchronized base site (,) based on the time difference of arrival of the signals received by the communication unit (,) from the base site (,) and at least one synchronized base site (,), the location of the communication unit (,), the location of the base site (,), and the location of the at least one synchronized base site (,).

Method and apparatus for performing a time synchronization of a base site

A frequency reference, a time reference and data may be provided on, and subsequently extracted from, a single information stream. To achieve this a modulator 102 generates the single information stream by modulating the data on the frequency reference and pre-empting the data modulation to modulate the time reference on the frequency reference. This single information stream is then provided on a single bus 106 which is coupled to a plurality of base stations 103-105. The base stations 103-105 each include a demodulator 107-109, which recovers the frequency reference 117, the time reference 118, and/or the data 116, from the single information stream.

Method for and apparatus to extract a frequency reference, a time

Data transfer for a time division multiplex (TDM) bus in a communication system that includes a plurality of communication nodes wherein each communication node is allocated at least one time slot of the TDM bus can utilize the following protocol to improve flexibility. When a communication node has an information packet to transmit, it must determine whether it is changing from a first information packet type to a second information packet type message. If a change from transmitting a first information packet type to transmitting a second information packet type is determined, an information type transition message is transmitted via the allocated time slot during a first frame cycle. Upon receiving the information type transition message, at least one other communication node stores the information type transition message. The transmitting communication node then transmits a second information packet type message during a subsequent frame cycle wherein a receiving communication node interprets the second information packet type message as a second information packet type.

Method for transmitting either data or voice in an allocated TDM slot

A phase lock loop (700) maintains a freewheeling capability while making phase corrections to a sample clock signal based on a precision timing signal. The phase corrections are dispersed over time such that data reception in uninterrupted so that data integrity is maintained during the phase corrections. The phase lock loop (700) includes a first divider circuit (721) having a divisor n, coupled for dividing the incoming clock signal by n to produce a bit clock signal. A second divider circuit (725) is coupled to the bit clock signal for dividing the bit clock signal to produce the sample clock signal. A phase comparator (717) is coupled to a 1PPS signal that provides a time-mark to said phase lock loop (700) for calibration, wherein the phase comparator (717) measures a number of input clock signal cycles from a predetermined edge of the 1PPS signal to a predetermined edge of the sample clock signal and provides a correction signal indicative of a number of input clock signal cycles and a phase direction error between the sample clock signal and the 1PPS signal for modifying a value of the divisor n for correcting the measured phase error simultaneously with data reception.

Autonomous pulse train timing controls for time-mark alignment

An addressing apparatus and method may be obtained in a data conveyance network by providing modular circuits with an addressing circuit and incorporating a coupling sense circuit. When a modular circuit is connected into the data conveyance modular network, the coupling sense circuit allows for a assignment token to be passed to the modular circuit such that the modular circuit can determine addresses of time slots which are to be allocated to it. The assignment token is only passed amongst the modular circuits at initial turn on of the data conveyance modular network or when a reset condition occurs which is triggered by a data conveyance controller.

Addressing method and apparatus for a data conveyance modular network

A data transfer network for computers is disclosed which combines characteristics of both multi-port memory devices and local area networks. Each computer is coupled to the network via a data terminal. The terminal permits the network to appear to the computers as random access memory. Data written into this RAM by the computers is formatted by the terminals into serial data packets, which are shifted around a serially connected ring or loop of the terminals. The loop connected terminals form the network.

Memory addressable data transfer network

An encryption key, required to encrypt and decrypt data according to a predefined algorithm is usually retained in a volatile memory device. Detection of loss of the key or corruption of the key is frequently possible only be means of the encryption circuit itself testing the key. Automated and repetitive testing of encryption keys by means of a processor or a control circuit periodically requesting the encryption circuit to test an encryption key minimizes data loss and system down time due to corrupted or lost keys.

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Wheaton, IL, United States of America

Mark G Spiotta