International Business Machines Corporation

Mark G Marshall

Patrick Edward Perry

Charles K Erdelyi

Scott Whitney Gould

John W Mathews

A wiring layout design method and system providing efficient routing of wiring paths between multiple function blocks in an integrated circuit is disclosed. Associated with the function blocks are logic service terminals (LSTs) aligned on-grid relative to the global wiring layout. The technique utilizes a locator designating a desired contact point for each on-grid LST to be connected. The contact point designation is made without restriction relative to the predetermined grid pattern of the logic service terminals. Subsequent use of a conventional global wiring layout program to generate a layout of connections between LSTs, a reformatting program connects each wired logic service terminal to its desired contact point on the associated function block using the corresponding locator.

Wiring layout design method and system for integrated circuits

A current limiting clamp circuit for providing a clamped voltage at a node and including a P-type MOS transistor and several N-type MOS transistors which are connected in series between the drain of the P-type MOS transistor and ground, with one of the N-type transistors having its gate and drain connected to the drain of the P-type transistor, and having its source connected to the node. In another embodiment, the current limiting clamp circuit includes a pair of P-type transistors and several N-type transistors, with one of the P-type transistors having its source connected to a power supply, its gate connected to ground and its drain connected to the source of the other P-type transistor which has its gate and drain connected to the node.

Current limiting clamp circuit

A delay circuit for receiving a number of input signals and for providing a delay in accordance with the input signals. The delay circuit includes: an output circuit for producing a first output signal when a node is above a threshold voltage, and for producing a second output signal, which is different from the first output signal, when the node is below the threshold voltage; a device for maintaining the node voltage at a level which is above the threshold voltage so that the output circuit produces the first output signal; and a plurality of switching devices for causing, the node voltage to decrease below the threshold voltage so that the output circuit produces the second output signal. Depending on which one of the switching devices is rendered conductive, the node voltage will decrease at a different rate, thereby causing the output circuit to produce the second output signal at different delay times.

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Essex Junction, VT, United States of America

Mark G Marshall