Matrix Semiconductor, Inc.

Sandisk 3D LLC

Rambus Inc.

Advanced Micro Devices Corporation

Discovery Laboratories, Inc.

Mark G Johnson

Thomas H Lee

James Montague Cleeves

Vivek Subramanian

Paul Michael Farmwald

Kevin S Donnelly

Chanh Vi Tran

N Johan Knall

Roy E Scheuerlein

Matthew P Crowley

P Michael Farmwald

Mark A Horowitz

Donald C Stark

Bruno Werner Garlepp

Benedict C Lau

Pak Shing Chau

Jun Y Kim

Igor G Kouznetsov

Leung Yu

J James Tringali

Derek Bosch

Yiu-Fai Chan

Nancy David Dillon, Legal Representative

Igor G Kouznetzov

Christopher John Petti

Brent Steven Haukness

Andrew J Walker

Tyler J Thorp

Alper Ilkbahar

John Bradly Dillon

Nhat M Nguyen

Bendik Kleveland

Luca Giovanni Fasoli

Joseph G Nolan, Iii

Brad Herner

S Brad Herner

John Christian Holst

Christopher S Moore

Tsyr-Chyang Ho

Roger March

Clemenz L Portmann

Johan Knall

Roy Coe

A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.

Three-dimensional nonvolatile memory and method of fabrication

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Dense arrays and charge storage devices

A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.

Pillar-shaped nonvolatile memory and method of fabrication

Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.

Silicon nitride antifuse for use in diode-antifuse memory arrays

A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

Vertically stacked field programmable nonvolatile memory and method of fabrication

In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.

Transceiver with latency alignment circuitry

A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Integrated circuit incorporating decoders disposed beneath memory arrays

Apparatus are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Apparatus for adaptive trip point detection

Methods are described for providing an adaptive trip point detector circuit that receives an input signal at an input signal node and generates an output signal at an output signal node, the output signal changing from a first value to a second value when the input signal exceeds a trip point reference value. In particular, the trip point reference value is adjusted to compensate for variations in process or temperature.

Methods for adaptive trip point detection

Three terminal nonvolatile memory device with vertical gated diode

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Los Altos, CA, United States of America

Mark G Johnson