Freescale Semiconductor,inc.

Everspin Technologies, Inc.

Motorola Corporation

Mark F Deherrera

Nicholas David Rizzo

Jason A Janesky

Mark A Durlam

Bradley Neal Engel

Gregory W Grynkewich

Brian R Butcher

Syed M Alam

Dimitri Houssameddine

Kelly Wayne Kyler

Thomas Andre

Jaynal Abedin Molla

Joseph J Nahas

Bradley J Garni

Jeffrey H Baker

Earl D Fuchs

John J D'Urso

J Jack Ren

Jon Michael Slaughter

Saied N Tehrani

Chitra K Subramanian

Eric John Salter

Steven M Smith

Bengt J Akerman

Anatoli A Korkin, Legal Representative

Leonid Savtchenko

Charles W Snyder

Thomas H Lee

Clarance J Tracy

Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.

Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines

Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.

Configuration and testing for magnetoresistive memory to ensure long term continuous operation

According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.

MRAM Memory conditioning

A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180&#xb0;. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.

Magneto resistance random access memory element

A method is provided for testing magnetic bits () of an array. A train of first (), second (), and third () pulses is provided to a desired bit, the first and second pulses beginning at a substantially similar low field and increasing in similar amounts with respect to successive trains of the first, second, and third pulses, the third pulse having a current amplitude sufficient to toggle the magnetic bit. A representative count is recorded in response to switching of the bit. The above steps are repeated and a determination is made of the current amplitude required to write and toggle the bit.

Triple pulse method for MRAM toggle bit characterization

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Cladded conductor for use in a magnetoelectronics device and method for fabricating the same

A direct write is provided for a magnetoelectronics information device that includes producing a first magnetic field with a first field magnitude in proximity to the magnetoelectronics information device at a first time (t). Once this first magnetic field with the first magnitude is produced, a second magnetic field with a second field magnitude is produced in proximity to the magnetoelectronics information device at a second time (t). The first magnetic field is adjusted to provide a third magnitude at a third time (t) that is less than the first field magnitude and greater than zero, and the second magnetic field is adjusted to provide a fourth field magnitude at a fourth time (t) that is less than the second field magnitude. This direct write is used in conjunction with other direct writes and also in combination with toggle writes to write the MRAM element without an initial read.

MRAM element and methods for writing the MRAM element

An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

MRAM architecture

A sense amplifier ( ) is provided for sensing the state of a toggling type magnetoresistive random access memory (MRAM) cell without using a reference. The sense amplifier ( ) employs a sample-and-hold circuit ( ) combined with a current-to-voltage converter ( ), gain circuit ( ), and cross-coupled latch ( ) to sense the state of a bit. The sense amplifier ( ), first senses and holds a first state of the cell. The cell is toggled to a second state. Then, the sense amplifier ( ) compares the first state to the second state to determine the first state of a toggling type memory cell.

Sense amplifier and method for performing a read operation in a MRAM

A method to switch a scalable magnetoresistive memory cell including the steps of providing a magnetoresistive memory device sandwiched between a word line and a digit line so that current waveforms can be applied to the word and digit lines at various times to cause a magnetic field flux to rotate the effective magnetic moment vector of the device by approximately 180&deg;. The magnetoresistive memory device includes N ferromagnetic layers that are anti-ferromagnetically coupled. N can be adjusted to change the magnetic switching volume of the device.

Method of writing to scalable magnetoresistance random access memory element

A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.

Growing community of inventors

Tempe, AZ, United States of America

Mark F Deherrera