International Business Machines Corporation

Mark Ernest Van Nostrand

Thomas Winters Fox

Charles Ray Johns

David Andrew Rice

Jeffrey Allan Whaley

Richard Anthony Marino

Cory Ansel Cherichetti

Joe Christopher St Clair

Javier A Rodriguez

Omar Mahmoud Rahim

Paul David Dinicola

A sphere mode texture coordinate generator circuit for use in a graphics adapter of a data processing system is disclosed. The circuit includes a set of input multiplexers configured to receive x, y, and z components of a normal vector and a unit vector corresponding to the current vertex. The circuit further includes a set of functional units such as a floating point multiplier, a floating point adder, a floating point compare-to-zero unit, and an inverse square unit. The functional units are configured to receive outputs from the set of multiplexer and are enabled to perform floating point operations on the outputs of the set of multiplexers. A controller or state machine of the circuit is enabled to determine the state of select inputs to each of the set of multiplexers. The controller manages the multiplexer select inputs such that the circuit determines sphere mode texture coordinates in response to receiving the normal vector and the unit vector. The circuit typically includes a set of latches, where the input of each of the latches is connected to an output of a corresponding input multiplexer. The circuit may include an S Out multiplexer and a T Out multiplexer, where the output of S Out multiplexer represents the S sphere mode texture coordinate and the output of the T Out multiplexer represents the T sphere mode texture coordinate calculated in compliance with a predetermined specification such as the OpenGL&reg; specification.

Sphere mode texture coordinate generator

A method and apparatus in a data processing system for processing graphics data in a processing element. A command is received. A determination is then made as to whether the command affects processing of current graphics data within the processing element. The command is sent to a subsequent processing element if the processing element is unaffected by the command. The command is held without affecting the processing element if the command affects processing of the current graphics data within the processing element until processing of the current graphics data has completed.

Method and apparatus for attribute processing with an active pipeline stage in a data processing system

A graphics pipeline receives graphics data at an input. Processed graphics data is transmitted at an output of the graphics pipeline. A plurality of stages are present in the graphics pipeline. A first stage within the plurality of stages is connected to the input and a last stage within the plurality of stages is connected to the output. A selected stage within the plurality of stages includes a plurality of modes of operation including a first mode of operation, responsive to receiving a first signal in which the selected stage is enabled to process graphics data received by the stage. A second mode of operation occurs in response to receiving a second signal, the selected stage is disabled and data received from a prior stage within the plurality of stages is passed through to a subsequent stage within the plurality of stages.

Programmable hardwired geometry pipeline

A computer system and an associated graphics adapter that includes one or more processors connected to a host bus. A system memory is accessible from the host bus via a memory controller and an I/O bridge is coupled between the host bus and an I/O bus. The computer system further includes a frame buffer suitable for storing a representation of a graphic image and the graphics adapter connected to the I/O bus. The graphics adapter includes means for receiving host pixel data that is formatted, according to a host format defining the ordering and width of a set host components, as a set of host component values. The adapter also has means for transforming the host pixel data into frame buffer pixel data where the frame buffer pixel data is formatted, according to a frame buffer format defining the ordering and width of a set of frame buffer components, as a set of frame buffer component values. In the preferred embodiment, the value of each host pixel data component is replicated in a corresponding component of the frame buffer pixel data by repeating the bits comprising the value in the corresponding frame buffer component until the frame buffer component is full. In the preferred embodiment, the transforming means includes a programmable set of host format definition registers that define the host format. These registers preferably include a start bit register and a width register for each component of the data. The component data widths are permitted to vary from one another in the preferred embodiment such that a first component of the host pixel data could have one width an a second component could have another (different) width. The adapter preferably further includes means for scaling and biasing the frame buffer pixel data and means for transforming (packing) frame buffer pixel data into host pixel data.

Pixel component packing, unpacking, and modification

Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.

Growing community of inventors

Cedar Park, TX, United States of America

Mark Ernest Van Nostrand