International Business Machines Corporation

University of Tennessee Research Foundation

Other

Mark Edward Dean

Gary Dale Carpenter

David Brian Glasco

Patrick M Bland

Ralph M Begun

Catherine Dorothy Schuman

J Douglas Birdwell

David William Boerstler

Hung Cai Ngo

Ronald Lynn Rockhold

Richard Nicholas Iachetta, Jr

Yoanna Baumgartner

Andrew Christian Zimmerman

Dennis L Moeller

Marc Raymond Faucher

Howard Carl Tanner

David A Kummer

Daniel Paul Beaman

Jesus A Saenz

Wendel Glenn Voigt

Anna Elman

James C Peterson

Margaret Grace Drouhard

James Stephen Fields, Jr

Kenneth Wayne Boyd

Kenneth Fairclough Day, Iii

John Jay Wolfgang

John Douglas Birdwell

Gene J Gaudenzi

Diana Joyce Hellman

Guy G Sotomayor

Thoi Nguyen

John Thomas Hollaway, Jr

James William Van Fleet

Kevin G Kramer

Philip E Milling

Lewis C Eggebrecht

Susan L Tempest

Sean Eugene Curry

James Michael Magee

John Peyton Bannister

Alvaro Eduardo Benavides

Philippe L De Backer

Philippe Louis deBacker

A method and apparatus for constructing one of a neuroscience-inspired artificial neural network and a neural network array comprises one of a neuroscience-inspired dynamic architecture, a dynamic artificial neural network array and a neural network array of electrodes associated with neural tissue such as a brain, the method and apparatus having a special purpose display processor. The special purpose display processor outputs a display over a period of selected reference time units to demonstrate a neural pathway from, for example, one or a plurality of input neurons through intermediate destination neurons to an output neuron in three-dimensional space. The displayed neural network may comprise neurons and synapses in different colors and may be utilized, for example, to show the behavior of a neural network for classifying hand-written digits between values of 0 and 9 or recognizing vertical/horizontal lines in a grid image of lines.

Method and apparatus for constructing a neuroscience-inspired artificial neural network with visualization of neural pathways

A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.

Method and apparatus for providing real-time monitoring of an artifical neural network

A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element or component thereof may be analog or digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse. The DANNA may thus form multiple levels of neuron and synapse circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the circuit element selectively functioning as one of a neuron and a synapse. The dynamic adaptive neural network array (DANNA) may comprise a special purpose processor for performing one of a control, anomaly detection and classification application and may comprise a first structure connected to a neuroscience-inspired dynamic artificial neural network (NIDA), comprise substructures thereof or be combined with other neural networks.

Method and apparatus for constructing a dynamic adaptive neural network array (DANNA)

A digital circuit element of a two dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the digital circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such digital circuit elements, a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse thus forming multiple levels of neuron and synapse digital circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the digital circuit element selectively functioning as one of a neuron and a synapse. The dynamic adaptive neural network array (DANNA) may implement long-term potentiation or depression to facilitate learning through the use of an affective system and random selection of input events.

Method and apparatus for providing random selection and long-term potentiation and depression in an artificial network

A method and apparatus for constructing a neuroscience-inspired artificial neural network (NIDA) or a dynamic adaptive neural network array (DANNA) or combinations of substructures thereof comprises one of constructing a substructure of an artificial neural network for performing a subtask of the task of the artificial neural network or extracting a useful substructure based on one of activity, causality path, behavior and inputs and outputs. The method includes identifying useful substructures in artificial neural networks that may be either successful at performing a subtask or unsuccessful at performing a subtask. Successful substructures may be implanted in an artificial neural network and unsuccessful substructures may be extracted from the artificial neural network for performing the task. The method and apparatus supports constructing, using and reusing components and structures of a neuroscience-inspired artificial neural network dynamic architecture in software and a dynamic adaptive neural network array.

Method and apparatus for constructing, using and reusing components and structures of an artifical neural network

A method and apparatus for constructing one of a neuroscience-inspired artificial neural network and a neural network array comprises one of a neuroscience-inspired dynamic architecture, a dynamic artificial neural network array and a neural network array of electrodes associated with neural tissue such as a brain, the method and apparatus having a special purpose display processor. The special purpose display processor outputs a display over a period of selected reference time units to demonstrate a neural pathway from, for example, one or a plurality of input neurons through intermediate destination neurons to an output neuron in three dimensional space. The displayed neural network may comprise neurons and synapses in different colors and may be utilized, for example, to show the behavior of a neural network for classifying hand-written digits between values of 0 and 9 or recognizing vertical/horizontal lines in a grid image of lines.

Data and metadata are generated in a computational device, wherein the generated data is stored in a first physical storage device coupled to the computational device, and wherein the generated metadata is stored transiently in the computational device. The data and the metadata are replicated to a second physical storage device. The replicated data and the replicated metadata in the second physical storage device are used to recover from a failure of at least one of the computational device and the first physical storage device.

Method, system and article of manufacture for metadata replication and restoration

A data storage device for recording to and reading from magnetic thread includes a head assembly having an opening through which the magnetic thread passes. Transducing elements are positioned around the inner surface of the opening and interact with longitudinally-extending parallel tracks formatted around the surface of the magnetic thread. If the number of tracks is greater than the number of transducing elements, the transducing elements may be rotatable about the magnetic thread to position the transducing elements to interact with other tracks. The head assembly may open to aid positioning the magnetic thread within the opening in the head assembly during loading. If desired, multiple head assemblies may be placed in the thread path to improve data throughput. The magnetic thread may be formed with a non-circular cross-section and the opening in the head assembly may have a corresponding cross-section to reduce twisting of the magnetic thread as it passes through the opening.

Data storage device for recording to magnetic thread

An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a &ldquo;time of day&rdquo; value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.

System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes

An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.

Apparatus and method for high resolution frequency adjustment in a multistage frequency synthesizer

An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.

Apparatus and method for dynamic frequency adjustment in a frequency synthesizer

A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In response to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node

A method and system in a distributed shared-memory data processing system are disclosed having a single operating system being executed simultaneously by a plurality of processors included within a plurality of coupled processing nodes for determining a utilization of each memory location included within a shared-memory included within each of the plurality of nodes by each of the plurality of nodes. The operating system processes a designated application utilizing the plurality of nodes. During the processing, for each of the plurality of nodes, a determination is made of a quantity of times each memory location included within a shared-memory included within each of the plurality of nodes is accessed by each of the plurality of nodes.

Method and system in a distributed shared-memory data processing system for determining utilization of shared-memory included within nodes by a designated application

A method for supporting software partition and dynamic reconfiguration within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes multiple nodes coupled to an interconnect. Each of the nodes includes a NUMA bridge, a local system memory, and at least one processor having at least a local cache memory. Multiple groups of software partitions are formed within the NUMA computer system, and each of the software partitions is formed by a subset of the nodes. A destination map table is provided in a NUMA bridge of each of the nodes for keeping track of the nodes within a software partition. A command is forwarded to only the nodes within a software partition.

Method and system for supporting software partitions and dynamic reconfiguration within a non-uniform memory access system

A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.

Reservation management in a non-uniform memory access (NUMA) data processing system

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Austin, TX, United States of America

Mark Edward Dean