Intel Corporation

Mark E Schuelein

Edward Butler

Charles E Dike

Aurobindo Dasgupta

Senthilkumar Jayapal

Deepak Bhatia

Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit, and an output, wherein the second memory unit operates on a second power supply which is always on; and a control logic coupled to the first and second memory units, the control logic to provide one or more control signals to each of the first and second memory units.

Low leakage state retention synchronizer

An apparatus may include a storage circuit that may have a first terminal and a second terminal and may have two cross-coupled inverters. The apparatus may include a feedback circuit coupled to the first terminal. The feedback circuit may include electronic logic elements to determine if the storage circuit is in a metastable state. The feedback circuit may couple at least one of the first and second terminals to one of a voltage reference and a voltage source if determined that the storage circuit is in a metastable state.

Latch with a feedback circuit

Disclosed herein are synchronization latch solutions.

Clock synchronizer

Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.

Logic with state retentive sleep mode

Method and apparatus for an ultra-drowsy circuit for use in lower power operational modes are described.

Ultra-drowsy circuit

A scan enabled storage device includes two storage elements and two input circuits. A data input circuit accepts a data signal, a clock signal, and a scan enable signal to inhibit the operation of the clock signal. A scan data input circuit accepts a scan data signal and a scan clock signal.

Scan enabled storage device

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage generator that selectively increases the voltage potential on the channel region of a transistor relative to the source region of the transistor. The voltage potential may be provided to a diffusion region in the well regions with transistors.

Apparatus and circuit having reduced leakage current and method therefor

An edge-triggered flip flop includes a clocking portion having first and second transistor stacks that are coupled to first and second storage nodes of a memory element, respectively. In at least one embodiment, a clock signal is applied to an input of at least one transistor in each stack and a delayed and possibly inverted version of the clock signal is applied to an input of at least one other transistor in each stack to clock new data into the memory element.

Slave-less edge-triggered flip-flop

In a gate array having a plurality of free transistors and target transistors, a method and apparatus for protecting a gate electrode of a target transistor from gate charge by employing a free transistor as a gate electrode protection device. A target transistor is a transistor that has been determined to need gate charging protection. A free transistor is a transistor in the gate array which is not used to implement the logic design as embodied in the gate array. Initially, a base array is formed without any metal layers. Then, a determination is made as to which transistors require gate charging protection. The gate electrode of each target transistor determined to require gate charging is coupled to an associated drain or source electrode of a free transistor of the gate array. The gate electrode of the free transistor is connected to an appropriate voltage reference to turn the free transistor off.

Method and apparatus for protecting gate electrodes of target

An improved storage circuit that allows multiple bits to be encoded and stored using a single storage element. The encoded information is defined by a coupling made between a transistor as the storage element and any one of several bit lines associated with the transistor. When the coupled bit line is discharged in response to a wordline signal, the stored information can be captured by an encoder. The circuit is particularly useful for efficiently storing information in a gate array integrated circuit, because the gate array has more space around each transistor to add bit lines than a conventional, densely packed, ROM.

Growing community of inventors

Tempe, AZ, United States of America

Mark E Schuelein