Conexant Systems, Inc.

Synaptics Corporation

Google Inc.

Mark E Miller

Trausti Thormundsson

David P Braun

Govind Kannan

Jeffrey Lukanc

Ali Abdollahzadeh Milani

Xuexin Liu

Bradley C Malemezian

Ganesha Tekkatte

Jens Kristian Poulsen

Chung-Jue Chen

Kenneth E Garey

Sudhaker Reddy Anumula

George Christopher Sneed

Shien-Tai Pan

Hari Hariharan

Harry Lau

David Dunn

Guy Rahamim

Christopher James Martin

Chilan T Nguyen

Randy Nuss

Ian Christopher Doidge

Ramakrishna Y Vadapalli

A docking station operable in a plurality of modes is disclosed. An example method includes obtaining first data via a first interface of the docking station configured to couple the docking station to a computing device and second data via a second interface of the docking station configured to communicate with a network, responsive to operating in a first mode, obtaining third data via the second interface of the docking station, responsive to operating in a second mode, and selectively outputting the first and the second data, or the third data, to a display based on whether the docking station operates in the first or the second mode. The selectively outputting includes determining that the computing device is not coupled to the docking station, and in response, processing the third data by an application installed in a secure sandbox, and outputting the processed third data to the display.

Third party applications for a network-capable docking station

A method performed by a docking station operable in a plurality of modes is disclosed. The method may include obtaining first data via a first interface of the docking station and second data via a second interface of the docking station, responsive to operating in a first mode of the plurality of modes. The first interface may be configured to couple the docking station to a computing device, and the second interface may be configured to communicate with a network. The method may also include obtaining third data via the second interface of the docking station, in lieu of the first interface, responsive to operating in a second mode of the plurality of modes. The method may further include selectively outputting the first data and the second data, or the third data, to a display based on whether the docking station operates in the first mode or the second mode.

Network-capable docking station

A time-of-flight sensor includes a light source to transmit periodic bursts light in a direction of one or more objects and an array of optical sensing elements to detect light reflected from the one or more objects and generate sensor data corresponding to the detected light. A distance calculator determines depth information of the one or more objects by determining a general phase shift of the reflected light relative to the transmitted light based on a first frame of the sensor data and a second frame of the sensor data, calculating an incremental phase shift of the reflected light relative to the transmitted light based on a linear relationship between the first frame and the second frame in relation to the general phase shift, and combining the general phase shift with the incremental phase shift to determine an actual phase shift of the reflected light relative to the transmitted light.

Derivation of depth information from time-of-flight (TOF) sensor data

Adaptive noise cancellation systems and methods comprise a reference sensor operable to sense environmental noise and generate a corresponding reference signal, an error sensor operable to sense noise in a noise cancellation zone and generate a corresponding error signal, a noise cancellation filter operable to receive the reference signal and generate an anti-noise signal to cancel the environmental noise in the cancellation zone, an adaptation module operable to receive the reference signal and the error signal and adaptively adjust the anti-noise signal, and a transient activity detection module operable to receive the reference signal, detect a transient noise event and selectively disable the adaptation module during the detected transient noise event.

Robust adaptive noise cancelling systems and methods

Systems and methods for low latency adaptive noise cancellation include an audio sensor to sense environmental noise and generate a noise signal, an audio processing path to receive an audio signal, process the audio signal through an interpolation filter, and generate a primary audio signal having a first sample frequency, an adaptive noise cancellation processor to receive the noise signal and generate an anti-noise signal, a direct interpolator to receive the anti-noise signal and generate an anti-noise signal having the first sample frequency, and a limiter to provide clipping to reduce a number of bits in the anti-noise signal, an adder operable to combine the primary audio signal and the anti-noise signal and generate a combined output signal, and a low latency filter to process the combined output signal.

Low delay decimator and interpolator filters

A system and a method provide for protecting a loudspeaker from thermal and/or mechanical failure by monitoring for over-temperature and over-power conditions. The system generates a first gain from a first speaker protection controller in response to a driving voltage and/or a driving current of a loudspeaker, and generates a second gain from a second speaker protection controller in response to the driving voltage and/or a driving current of the loudspeaker, if the temperature exceeds a thermal limit or if the power exceeds a maximum power. The system applies the second gain to an audio signal to lower the audio signal if the first speaker protection controller fails.

Non-linear feedback control for temperature and power protection of loudspeakers

Encrypted storage often introduces unwanted latency in access. This delay can result in a processor having to wait for critical data thus slowing performance. Generally speaking, the latency is at most an issue when reading from encrypted storage, since the processor may need the information read from encrypted storage to proceed. During a write operation, there typically is not an issue because the processor does not need to wait for the end of the write operation to proceed. A variant of counter (CTR) mode for a block cipher can be used to perform the majority of the decryption operation without knowledge of the ciphertext, therefore the majority of the decryption operation can be performed concurrently with the retrieval of the ciphertext from memory. In order to further secure the encrypted storage, a light encryption can be performed to further obfuscate the ciphertext.

Systems and methods for low-latency encrypted storage

A system for controlling a touch screen. A touch screen element having a plurality of contacts, such as one contact electrode at each of four corners. A multiplexer coupled to the touch screen element for forming a plurality of connections, such as various combinations of the contact electrodes to allow measurements to be made of the impedance of the touch screen element from the left side to the right side, from the top to the bottom, and do forth. A touch screen processor coupled to the touch screen element for determining an oscillation frequency of the touch screen element as a function of the electrode connections.

Adaptive high dynamic range surface capacitive touchscreen controller

This disclosure provides systems and methods for detecting a change in environmental conditions utilizing sampling circuitry configured to sample an environmental sensor while a processor remains in a low-power state or a sleep state. According to some embodiments, a pre-filter performs a simplified analysis of the sensor samples to determine if the processor should wake and perform additional analysis on stored sensor samples. Specific examples are provided for detecting motion using passive infrared detectors. Accordingly, systems and methods for reducing the power consumption of a motion detection system are provided herein.

Multi-sample reading in sleep mode for passive infrared detectors and other analog inputs

Multi-level cell (MLC) flash memory has become widely used due to their capacity to store more information in the same area as a single-level cell (SLC) flash memory. This makes MLC flash memory very attractive for storing media. Flash has also traditionally been used in electronic devices for firmware, but MLC flash is less reliable than SLC flash. For critical memory operations, MLC flash memory can be made as reliable as SLC flash by mapping one binary value to an MLC state corresponding to the highest threshold voltage and the other binary value to the MLC state corresponding the lowest threshold voltage when writing to the MLC flash, and by mapping all MLC states with corresponding threshold voltages above a central cutoff threshold voltage to one binary value and by mapping all MLC states with corresponding threshold voltages below a central cutoff threshold voltage to the other binary value.

Systems and methods for reliable multi-level cell flash storage

Presently disclosed is method and apparatus for generating a random bit stream by generating a random bit according to a polynomial expression, providing a modification function operative on the polynomial expression, and modifying the polynomial expression by modifying the modification function.

Method and apparatus for generating a random bit stream

There is provided a method of modifying a first clock to generate a second clock with reduced electromagnetic interference (EMI). The method comprises receiving the first clock, generating an upslew modulation form during an upslew frequency transition, generating a downslew modulation form during a downslew frequency transition, modulating a frequency of the first clock over a period of time using the upslew modulation form and the downslew modulation form to generate the second clock, and wherein the upslew modulation form and the downslew modulation form are different. The upslew modulation form and the downslew modulation form are defined by upslew modulation values and downslew modulation values, respectively, and the method further comprises receiving the upslew modulation values and the downslew modulation values, and generating fractional upslew modulation values and fractional downslew modulation, respectively, for modulating the frequency of the first clock.

Spread spectrum clock generation

Packet-Based Direct Memory Access. The present invention overcomes the oftentimes hardware consumptive and complex implementation of conventional direct memory access (DMA) that employs descriptors. The descriptors that must are employed by conventional DMA must be set up by software, and the handshaking between the hardware and software is typically very cumbersome. The packet-based DMA performed in accordance with the present invention is operable and adaptable to various types of cell-based DMA modes. A flow control regulator, or flow control state machine, is used to control the packet-based DMA performed in accordance with the present invention. Two different multiplexors (MUXs) are employed, one for each of the transmit and the receive packet-based DMA transfers, to select the various cases of packet-based DMA. The present invention is operable within various modes including asynchronous transfer mode (ATM) cell-based asynchronous digital subscriber loop (ADSL) applications. An efficient implementation using registers to control the packet-based DMA transfers is provided by the present invention.

Packet-based direct memory access

In one embodiment, a single designated register in a codec is utilized by a controller to address and control a large number of expansion registers belonging to various expansion devices. The controller can write to or read from the designated register through an AC-link while complying with the AC '97 specification. The address and data bits in the designated register are used to write to or read from a target register in an expansion device. The designated register is selected from one of the registers available to a design engineer in accordance with the AC '97 specification. An example of an expansion device that can be addressed and controlled through the designated register is an SSD device. In another embodiment, two designated registers in the codec register set are utilized. The controller can write address information into one of the designated registers while complying with the AC '97 specification. The controller can also write data to or read data from the other designated register through the AC-link while complying with the AC '97 specification. The address and data bits in the designated registers are used to write to or read from a target register in an expansion device. The two designated registers are selected from the 16 registers available to a design engineer in accordance with the AC '97 specification.

Method and apparatus for addressing and controlling exspansion devices through an AC-link and a codec

A method and apparatus for facilitating AC-link communications between a controller and a slow peripheral of a codec is disclosed. In one embodiment, the GPIO_INT bit (i.e. bit in slot in the AC-link's SDATA_IN line) is utilized as an interrupt flag to indicate when data requested by the controller from the slow peripheral is returned and is available to be read by the controller. The GPIO_INT bit can also be used to indicate when a write into the slow peripheral is completed. In this embodiment, a &ldquo;peripheral ready bit&rdquo; or a &ldquo;peripheral ready signal&rdquo; originated from the slow peripheral is used to set the GPIO_INT bit. Another embodiment is directed to controllers which ignore the GPIO_INT bit as a source of interrupt. To accommodate these controllers, one of the GPIO bits is used to send the value of the &ldquo;peripheral ready bit&rdquo; to the controller. Upon receipt of the peripheral ready bit as one of the GPIO bits from the codec, the controller would interrupt the host CPU and the host CPU is made aware that the data requested from the slow peripheral is returned and is available to be read. The GPIO bit can also be used to indicate that a write into the slow peripheral has been completed. In yet another embodiment, the software running on the host CPU successively checks the peripheral ready bit, which is a designated bit in one of the codec's vendor reserved registers, to find out when the peripheral ready bit has been set. When the peripheral ready bit is set, and so detected by the software, the software would be alerted to the fact that the register from which data was requested now contains the requested data, and the requested data is then read by the software. The designated bit can also be used to indicate that a write into the slow peripheral has been completed.

Growing community of inventors

Mission Viejo, CA, United States of America

Mark E Miller