Infineon Technologies Richmond, LP

Mark E Luzar

Robert Petter

Michael Bernhard Sommer

Joerg W Wohlfahrt

Ulrich Zimmermann

Dieter Rathei

Luis G Andrade

Violetta Schlesinger

Babatunde Ashiru

Thomas S Taylor

A method of calculating yield loss of semiconductor wafers which are tested with a test sequence to derive a total fail region count for each of the wafers, the semiconductor wafers having multiple chips thereon. The method comprises calculating a fail region count for each of the tests in the test sequence, calculating the test sequence limited yield loss for each of the wafers, and apportioning the test sequence limited yield loss to selected ones of the test based upon the absolute or cumulative number of fails identified by the tests of the test sequence. In some embodiments, core parametric test data is correlated with the test sequence limited yield and analyzed to determine reparability.

Method for semiconductor yield loss calculation

A deep trench capacitor, in accordance with the present invention, includes a deep trench formed in a substrate having a storage node formed therein. A center node is capacitively coupled to the storage node. The center node is disposed within the deep trench and formed inside the storage node. A first buried strap is provided for accessing the storage node, and a second buried strap is electrically isolated from the storage node and formed in contact with the center node and a buried plate. The center node is formed to provide additional capacitive area to the deep trench capacitor. A method for forming the deep trench capacitor in accordance with the present invention is also provided.

Folded deep trench capacitor and method

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Chester, VA, United States of America

Mark E Luzar