Intel Corporation

Micron Technology Incorporated

Lattice Semiconductor Corporation

Mark E Bauer

Sherif R Sweha

Albert Fazio

Sanjay S Talreja

Robert L Baltar

Sandeep K Guliani

Ritesh B Trivedi

Kevin W Frary

Matthew David Rowley

Balaji Srinivasan

Johnny Javanifard

Gregory E Atwood

Phillip M Kwong

Steven E Wells

Kerry Dean Tedrow

Robert N Hasbun

Rodney R Rozman

Mamun Ur Rashid

Mark J Christopherson

Phil Kliza

Hernan Adolfo Castro

Hari Giduturi

Duane R Mills

Peter K Hazen

Richard D Pashley

Greg Atwood

Mark D Winston

David M Brown

Stephen N Keeney

Gregg R Josephson

George R Canepa

Chakravarthy Yarlagadda

Michel I Ishac

Steven D Pudar

George Blanchard

Glen Hawk

Gary J Gallagher

Ken Wojciechowski

Balajl Srinivasan

A memory device includes a communication circuit configured to communicate a first signal and a second signal; and a selection mechanism coupled to the communication circuit and configured to select between operating the communication circuit the first signal and the second signal (1) independent signals for separate memory operations or (2) a complementary set for a memory operation.

Memory device with a multi-mode communication mechanism

A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.

Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array

A current sensing scheme for non-volatile memory is disclosed comprising an apparatus for determining one or more memory cell states in a non-volatile memory device. The apparatus having a first memory cell coupled to a first bitline and a first sensing element coupled to the first bitline, the first sensing element operable to sense a voltage corresponding to a state of the memory cell wherein the sensed voltage is independent of a bitline voltage discharge over time of the first memory cell.

Current sensing scheme for non-volatile memory

A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal.

Two transistor wordline decoder output driver

In one embodiment, a method and apparatus for reading one block of a nonvolatile memory device while writing to another block of a nonvolatile memory device is disclosed.

Block-level read while write method and apparatus

An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal, providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.

Kicker for non-volatile memory drain bias

An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.

Load for non-volatile memory drain bias

An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

Drain bias for non-volatile memory

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. &ldquo;By-output&rdquo; architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. &ldquo;By-address&rdquo; architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

Bit map addressing schemes for flash memory

Growing community of inventors

Cameron Park, CA, United States of America

Mark E Bauer