Advanced Micro Devices Corporation

Nvidia Corporation

Ati Technologies Ulc

Globalfoundries Inc.

Other

Data General Corporation

Api Networks, Inc.

Alpha Processor, Inc.

Alliance Semiconductor Corporation

Advanced Micro Device, Inc.

Onesta Ip, LLC

Mark Douglas Hummel

Anthony Asaro

David E Mayhew

Andrew William Lueck

Andrew Gregory Kegel

Glenn A Dearth

Michael J Osborn

Geoffrey S Strongin

Kevin B Normoyle

Jonathan Mercer Owen

Mitchell K Alsup

Michael Haertel

James B Keller

Samuel Hammond Duncan

Derrick R Meyer

Stephen David Glaser

Jonathan Owen

Olivier Giroux

Philip J Rogers

Denis J Foley

Larry Robert Dennison

Vyas Venkataraman

Eric Tyson

Benjamin Charles Serebrin

Gerald Robert Talbot

Marvin A Denman

Dennis K Ma

Anton Chernoff

Nan Jiang

Venkata Krishnan

David I Epstein

Mike Osborn

Michael Osborn

Gregory Michael Thorson

David A Kaplan

Mark Fowler

Warren Fritz Kruger

Alexander Lev Minkin

Wishwesh Anil Gandhi

Rodney W Schmidt

Sanjeev Jain

Michael A Parker

John R Feehrer

Paul Blinzer

Brian Kelleher

Manan Patel

Gongxian Jeffrey Cheng

Erich Boleyn

Ram Gummadi

Hemayet Hossain

Raghuram L

Alexander Toichi Ishii

Daniel Joseph Lustig

Srinivas Santosh Kumar Madugula

John Wortman

Dale E Gulick

Philip Ng

Larry David Hewitt

Frederick Daniel Weber

William Alexander Hughes

Mauricio Breternitz, Jr

David I J Glen

Eitan Zahavi

Gil Bloch

Rex Eldon McCrary

Gordon Caruk

Michael Ignatowski

R Stephen Polzin

James Marriot Guyer

Miriam Menes

Benedict R Gaster

Steven J Wallach

Michael C Houston

Paul C Miranda

Jeffrey Gongxian Cheng

Lee W Howes

Dane Mrazek

Shwetal Arvind Patel

Richard W Reeves

Ross Voigt La Fetra

Stephen Patrick Thompson

Elizabeth Morrow Cooper

Norman Rubin

David L Keating

Denis Rystsov

Ahmad Atamli

Karan Gupta

Rex Eldon Mccrary

John F Wiederhirn

Michael A Pogue

Morgan J Dempsey

Shreyaunsh R Shah

Leo C Waible, Iii

Donald C Wiser

Rona J Newmark

Peter C Bixby

Rosemarie Alicandro

Paul W Woodbury

Eric H Enberg

Paul K Marino

Various embodiments include techniques for performing self-synchronizing remote memory operations in a multiprocessor computing system. During a remote memory operation in the multiprocessor computing system, a source processing unit transmits multiple segments of data to a destination processing. For each segment of data, the source processing unit transmits a remote memory operation to the destination processing unit that includes associated metadata that identifies the memory location of a corresponding synchronization object. The remote memory operation along with the metadata is transmitted as a single unit to the destination processing unit. The destination processing unit splits the operation into the remote memory operation and the memory synchronization operation. As a result, the source processing unit avoids the need to perform a separate memory synchronization operation, thereby reducing inter-processor communications and increasing performance of remote memory operations.

Self-synchronizing remote memory operations in a multiprocessor system

A method is provided for operating a network switch comprising a plurality of input ports and a plurality of output ports. The method comprises receiving a first data packet received via a first input port and a second data packet received via a second input port to be delivered to an egress endpoint connected to a first output port, configuring a plurality of crossbar switch units arranged in a tiled architecture to pass the first data packet to the first output port via a primary path and pass the second data packet to the first output port via a secondary path, and transmitting the first data packet and the second data packet to the egress endpoint. The first data packet and the second data packet pass through the plurality of crossbar switch units simultaneously.

Crossbar multipathing for multicast performance in tiled switches

A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Memory pools in a memory model for a unified computing system

In various examples, a single notification (e.g., a request for a memory access operation) that a processing element (PE) has reached a synchronization barrier may be propagated to multiple physical addresses (PAs) and/or devices associated with multiple processing elements. Thus, the notification may allow an indication that the processing element has reached the synchronization barrier to be recoded at multiple targets. Each notification may access the PAs of each PE and/or device of a barrier group to update a corresponding counter. The PEs and/or devices may poll or otherwise use the counter to determine when each PE of the group has reached the synchronization barrier. When a corresponding counter indicates synchronization at the synchronization barrier, a PE may proceed with performing a compute task asynchronously with one or more other PEs until a subsequent synchronization barrier may be reached.

Efficient multi-device synchronization barriers using multicasting

In various examples, a memory model may support multicasting where a single request for a memory access operation may be propagated to multiple physical addresses associated with multiple processing elements (e.g., corresponding to respective local memory). Thus, the request may cause data to be read from and/or written to memory for each of the processing elements. In some examples, a memory model exposes multicasting to processes. This may include providing for separate multicast and unicast instructions or shared instructions with one or more parameters (e.g., indicating a virtual address) being used to indicate multicasting or unicasting. Additionally or alternatively, whether a request(s) is processed using multicasting or unicasting may be opaque to a process and/or application or may otherwise be determined by the system. One or more constraints may be imposed on processing requests using multicasting to maintain a coherent memory interface.

Multicast and reflective memory behavior for memory model consistency

Systems and techniques for performing multicast-reduction operations. In at least one embodiment, a network device receives first network data associated with a multicast operation to be collectively performed by at least a plurality of endpoints. The network device reserves resources to process second network data to be received from the endpoints, and sends the first network data to a plurality of additional network devices. The network device receives the second network data, and processes the second network data using the reserved resources.

Multicast-reduction assisted by network devices

Apparatuses, systems, and techniques are presented to configure computing resources to perform various tasks. In at least one embodiment, an approach presented herein can be used to verify whether a network of computing nodes is properly configured based, at least in part, on one or more expected data strings generated by the network of computing nodes.

Path attestation for computing resources

Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Techniques for an efficient fabric attached memory

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Multiprocessor clusters in a virtualized environment conventionally fail to provide memory access security, which is frequently a requirement for efficient utilization in multi-client settings. Without adequate access security, a malicious process may access what might be confidential data that belongs to a different client sharing the multiprocessor cluster. Furthermore, an inadvertent programming error in the code for one client process may accidentally corrupt data that belongs to the different client. Neither scenario is acceptable. Embodiments of the present disclosure provide access security by enabling each processing node within a multiprocessor cluster to virtualize and manage local memory access and only process access requests possessing proper access credentials. In this way, different applications executing on a multiprocessor cluster may be isolated from each other while advantageously sharing the hardware resources of the multiprocessor cluster.

Securing memory accesses in a virtualized environment

Introduced herein is a routing technique that, for example, routes a transaction to a destination port over a network that supports link aggregation and multi-port connection. In one embodiment, two tables that can be searched based on the target and supplemental routing IDs of the transaction are utilized to route the transaction to the proper port of the destination endpoint. In an embodiment, the first table provides a list of available ports at each hop/route point that can route the transaction to the destination endpoint, and the second table provides a supplemental routing ID that can select a specific group of ports from the first table that can correctly route the transaction to the proper port.

Network routing using aggregated links

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.

Multiple processors are often used in computing systems to solve very large, complex problems, such as those encountered in artificial intelligence. Such processors typically exchange data among each other via an interconnect fabric (such as, e.g., a group of network connections and switches) in solving such complex problems. The amount of data injected into the interconnect fabric by the processors can at times overwhelm the interconnect fabric preventing some of the processors from communicating with each other. To address this problem, techniques are disclosed to enable, for example, processors that are connected to an interconnect fabric to coordinate and control the amount of data injected so that the interconnect fabric does not get overwhelmed.

Techniques for reducing congestion in a computer network

Growing community of inventors

Franklin, MA, United States of America

Mark Douglas Hummel