Altera Corporation

Mark Dickinson

Edward H Flaherty

Roger May

Igor Kostarnov

James Tyson

The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same I/O pins. The data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by a control signal that determines when particular I/O pins are accessed by the programmable logic portion and the embedded processor portion. Control signals that configure the associated I/O pin circuitry to the correct I/O standard are also multiplexed by the shared I/O circuitry of the present invention. Signals received at the shared I/O pins that are transmitted to the embedded processor portion may be concurrently sent to snoop circuitry within the programmable logic portion.

I/O circuitry shared between processor and programmable logic portions of an integrated circuit

An integrated circuit includes programmable logic circuitry and control circuitry that is operable to enable the integrated circuit to make a connection to an external source of data for configuring the programmable logic circuitry. The integrated circuit may include dedicated communications port circuitry that can be used in making the above-mentioned connection, or the programmable logic circuitry itself can be configured for operation as communications port circuitry for use in making the connection. The programmable logic circuitry may be configured any number of times.

Configuration and/or reconfiguration of integrated circuit devices that include programmable logic and microprocessor circuitry

A programmable logic device is reconfigurable between two functionalities, while it is in use. The programmable logic device has a first store, into which configuration data may be downloaded from an external memory device, and a second store, in which a copy of the configuration data is maintained, with the functionality of the programmable logic device being determined by the copy of the configuration data, thereby allowing additional configuration data to be downloaded from the external memory device into the first store, while maintaining the functionality of the device. This allows the device to be used to provide two different functionalities, and to be switched between these two functionalities with minimal delay for reconfiguration of the device.

Updating configuration for programmable logic device

A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.

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Brill, United Kingdom

Mark Dickinson