Kla Tencor Corporation

Kla Corporation

International Business Machines Corporation

Kla-tencor Technologies Corporation

Other

Mark Davis Smith

Myungjun Lee

Ady Levy

John Joseph Biafore

John S Graves

Michael E Adel

Roel Gronheid

David A Blankenship

Franz Zach

Vladimir Levinski

Stilian Pandev

Daniel Kandel

Eran Amit

Pradeep Vukkadala

Franz X Zach

Pradeep Subrahmanyan

Dieter Mueller

David B Owen

Prasanna Dighe

William Pierson

Onur Demirer

Jason Saito

Xiaomeng Shen

Jeremy Nabeth

Stuart Sherwin

Sanjay Kapasi

Stewart A Robertson

Fatima Anis

Amnon Manassen

Sandeep Madhav Uttamchandani

Nagapramod S Mandagere

Pin Zhou

Walter Dean Mieher

Brian Duffy

Chris Mack

Seshashayee Sankarshana Murthy

Daria Negri

Yuri Paskover

Mark Wagner

Amir Widmann

Lynn H Smith

Chao Fang

Yuval Lubashevsky

Mike Adel

Eitan Hajaj

Dzmitry Sanko

Tal Itzkovich

Sharon Aharon

Aviv Frommer

Jose Enrique Solomon

Elyakim Kassel

Hoyoung Heo

Jeffrey Byers

Ramkumar Karur-Shanmugam

Christian Sparka

Alessandro Vaglio Pret

Miguel Garcia-Medina

Lipkong Yap

Choon (George) Hoong Hoo

Robert Hardister

Mike Pochkowski

Onur Nihat Demirer

Thomas Breymeier

Dee R Smith

John J Biafore

Trey S Graves

David Blankenship

A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform stress-free shape measurements on an active wafer, a carrier wafer, and a bonded device wafer. The active wafer includes functioning logic circuitry and the carrier wafer is electrically passive. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements; determine overlay distortion between features on the active wafer and the carrier wafer; and convert the overlay distortion to a feed-forward correction for one or more lithographic scanners. The controller is also configured to determine a control range for a bonder or lithography scanner; predict an overlay distortion pattern; calculate an optimal control signature based on a minimal achievable overlay; and provide a feed-forward correction to the bonder or lithography scanner based on the calculated optimal control signature.

System and method for optimizing through silicon via overlay

A wafer shape metrology system includes a wafer shape metrology sub-system configured to perform one or more stress-free shape measurements on a first wafer, a second wafer, and a post-bonding pair of the first and second wafers. The wafer shape metrology system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller is configured to receive stress-free shape measurements from the wafer shape sub-system; predict overlay between one or more features on the first wafer and the second wafer based on the stress-free shape measurements of the first wafer, the second wafer, and the post-bonding pair of the first wafer and the second wafer; and provide a feedback adjustment to one or more process tools based on the predicted overlay. Additionally, feedforward and feedback adjustments may be provided to one or more process tools.

System and method for determining post bonding overlay

A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.

System and method for mitigating overlay distortion patterns caused by a wafer bonding tool

Metrology methods, modules and targets are provided, for measuring tilted device designs. The methods analyze and optimize target design with respect to the relation of the Zernike sensitivity of pattern placement errors (PPEs) between target candidates and device designs. Monte Carlo methods may be applied to enhance the robustness of the selected target candidates to variation in lens aberration and/or in device designs. Moreover, considerations are provided for modifying target parameters judiciously with respect to the Zernike sensitivities to improve metrology measurement quality and reduce inaccuracies.

Metrology target design for tilted device designs

A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.

Process-induced displacement characterization during semiconductor production

An overlay control system is disclosed. In embodiments, the system may include a controller configured to: acquire a set of feedback overlay measurements based on a plan of record (POR) sampling map on a second layer of samples of at least one previous lot of samples; generate a reference wafer overlay map based on the set of feedback overlay measurements; acquire a set of feedforward overlay measurements based on a feedforward sampling map on a first layer of a set of samples of a current lot of samples; generate a set of artificial overlay vector maps for the set of samples of the current lot of samples based on the set of feedforward overlay measurements; and cause a lithography tool to fabricate a second layer of samples of the current lot of samples based on the reference wafer overlay map and the set of artificial overlay vector maps.

System and method for wafer-by-wafer overlay feedforward and lot-to-lot feedback control

Metrology methods are provided, which comprise identifying overlay critical patterns in a device design, the overlay critical patterns having an overlay sensitivity to process variation above a specified threshold that depends on design specifications; and using metrology targets that correspond to the identified overlay critical patterns. Alternatively or complementarily, metrology methods comprise identifying yield critical patterns according to a corresponding process window narrowing due to specified process variation, wherein the narrowing is defined by a dependency of edge placement errors (EPEs) of the patterns on process parameters. Corresponding targets and measurements are provided.

Metrology using overlay and yield critical patterns

Metrology targets and target design methods are provided, in which target elements are defined by replacing elements from a periodic pattern having a pitch p, by assist elements having at least one geometric difference from the replaced elements, to form a composite periodic structure that maintains the pitch p as a single pitch. Constructing targets within the bounds of compatibility with advanced multiple patterning techniques improves the fidelity of the targets and fill factor modulation enables adjustment of the targets to produce sufficient metrology sensitivity for extracting the overlay while achieving process compatibility of the targets.

Process compatibility improvement by fill factor modulation

A metrology system includes a controller communicatively coupled to a metrology tool. The controller may generate a three-dimensional model of a sample, generate a predicted metrology image corresponding to a predicted analysis of the sample with the metrology tool based on the three-dimensional model, evaluate two or more candidate metrology recipes for extracting the metrology measurement from the one or more predicted metrology images, select, based on one or more selection metrics, a metrology recipe from the two or more candidate metrology recipes for extracting a metrology measurement from an image of the structure from the metrology tool, receive an output metrology image of a fabricated structure from the metrology tool based on a metrology measurement of the fabricated structure, and extract the metrology measurement associated with the fabricated structure from the output metrology image based on the metrology recipe.

Metrology recipe generation using predicted metrology images

A system is disclosed. The system includes a tool cluster. The tool cluster includes a first deposition tool configured to deposit a first layer on a wafer. The tool cluster additionally includes an interferometer tool configured to obtain one or more measurements of the wafer. The tool cluster additionally includes a second deposition tool configured to deposit a second layer on the wafer. The tool cluster additionally includes a vacuum assembly. One or more correctables configured to adjust at least one of the first deposition tool or the second deposition tool are determined based on the one or more measurements. The one or more measurements are obtained between the deposition of the first layer and the deposition of the second layer without breaking the vacuum generated by the vacuum assembly.

System and method for process-induced distortion prediction during wafer deposition

A process control system includes a controller configured to generate a reference overlay signature based on one or more overlay reference layers of a sample, extrapolate the reference overlay signature to a set of correctable fields for the exposure of a current layer of the sample to generate a full-field reference overlay signature, identify one or more alignment fields of the set of correctable fields, generate an alignment-correctable signature by modeling alignment corrections for the set of correctable fields, subtract the alignment-correctable signature from the full-field reference overlay signature to generate feedforward overlay corrections for the current layer when the one or more overlay reference layers are the same as the one or more alignment reference layers, generate lithography tool corrections based on the feedforward overlay corrections, and provide the lithography tool corrections for the current layer to the lithography tool.

Layer-to-layer feedforward overlay control with alignment corrections

A semiconductor tool includes an illumination source to generate an illumination beam, one or more illumination optical elements to direct a portion of the illumination beam to a sample, a detector, one or more collection optical elements to direct radiation emanating from the sample to the detector, and a controller communicatively coupled to the detector. The controller is configured to measure alignment at a plurality of locations across the sample to generate alignment data, select an analysis area for alignment zone determination, divide the analysis area into two or more alignment zones having different alignment signatures; model the alignment data of at least a first alignment zone of the two or more alignment zones using a first alignment model, and model the alignment data of at least a second alignment zone of the two or more alignment zones using a second alignment model different than the first alignment model.

Systems and methods for automated multi-zone detection and modeling

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Austin, TX, United States of America

Mark Davis Smith