Western Digital Technologies, Inc.

Mark David Myran

Chandan Mishra

Amir Hossein Gholamipour

Namhoon Yoo

Jun Tao

Steven Theodore Sprouse

James M Higgins

Aldo Giovanni Cometti

David George Dreyer

Rodney Brittner

Matias Bjorling

Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

Logical to physical mapping management using low-latency non-volatile memory

The present disclosure generally relates to data storage devices, such as solid state drives. The data storage device includes a controller that includes a compression engine. The controller receives a ZNS append command to write data to a media, such as a non-volatile memory. The compression engine compresses data from a first number of logical blocks to second number of logical blocks. The compressed data is programmed to the media. The compressed data has a media logical block address and a host logical block address, where the media logical block address is the actual LBA where the ZNS append places the data on the media and the host logical block address is the location of the data stored on the media from the host's point of view. The host generates an index of the location of the stored data and the controller programs the index to the relevant location in the media.

Host-managed hardware compression with zoned namespaces

Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

Solid state drive using two-level indirection architecture

The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Scaling large drives using enhanced DRAM ECC

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Trabuco Canyon, CA, United States of America

Mark David Myran