Fujitsu Semiconductor Limited

Synopsys, Inc.

Synopys, Inc.

Mark David Lippett

Ayewin Oung

A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing resources for processing executable transactions, at least one of said elements being a master processing unit, the controller being adapted to communicate, when installed, with each of the processor elements including the master processing unit, and comprising control logic for allocating executable transactions within the multicore processor to particular processor elements in accordance with pre-defined allocation parameters.

Resource management in a multicore architecture

A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

Debug in a multicore architecture

This invention relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

Scheduling in a multicore architecture

The disclosure relates to scheduling threads in a multicore processor. Executable transactions may be scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

According to a first aspect of the present invention, there is provided a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators indicative of one or more parameters relating to the function and/or identity of a thread or threads comparing at least some of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

A method and computer-usable medium including instructions for performing a method for scheduling executable transactions within a multicore processor comprising a plurality of processor elements. The method includes listing, using at least one distribution queue, a portion of the executable transactions in order of eligibility for execution. A plurality of executable transaction schedulers are provided, wherein each executable transaction scheduler includes a scheduling process for determining a most eligible executable transaction for execution from at least one candidate executable transaction ready for execution. The executable transaction schedulers are linked together to provide a multilevel scheduler. The most eligible executable transaction is output from the multilevel scheduler to the at least one distribution queue.

Scheduling in a multicore processor

A method and computer-usable medium including instructions for performing a method of managing power consumption in a multicore processor comprising a plurality of processor elements with at least one power saving mode. The method includes listing, using at least one distribution queue, a portion of the executable transactions in order of eligibility for execution. A plurality of executable transaction schedulers are provided. The executable transaction schedulers are linked together to provide a multilevel scheduler. The most eligible executable transaction is output from the multilevel scheduler to the at least one distribution queue. One or more of the plurality of processor elements are placed into a first power saving mode when a number of executable transactions allocated to the plurality of processor elements is such that only a portion of available processor elements are used to execute executable transactions.

Managing power consumption in a multicore processor

A method and apparatus for resource management in a multicore processor is disclosed. A system management controller () provides omnipresent scheduling, synchronization, load balancing, and power and memory management services to each processing resource () within in a multicore processor (), via a plurality of system management clients () implemented in hardware or software. The controller () allocates the tasks executing in each processing resource () by means of interrupt control signals, which interact directly with the system management clients (), enabling processing resources () to autonomously create, execute and distribute tasks around a parallel system architecture whilst monitoring and policing the use of shared system resources ().

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Watlington, United Kingdom

Mark David Lippett