International Business Machines Corporation

Globalfoundries Inc.

Other

Mark David Jacunski

John Atkinson Fifield

Toshiaki Kirihata

Eric D Hunt-Schroeder

William R Tonti

Darren Lane Anand

Thomas M Maffitt

Alan D Norris

Russell J Houghton

Matthew R Wordeman

Gregory J Fredeman

John W Golz

David G Chapman

Nicholas Martin Van Heel

Michael A Killian

David E Douse

Pooja R Batra

Samuel K Weinstein

John Edward Barth, Jr

Wayne Frederick Ellis

Paul Christian Parries

Kevin William Gorman

Ciaran J Brennan

Kevin McStay

Jonathan R Fales

Nicholas Van Heel

Matthew C Lanahan

A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

Latching current sensing amplifier for memory array

Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.

On-chip reliability monitor and method

Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control logic and a second node connected to a field effect transistor (FET) diode stack, a plurality of boot enabled transistors which each contain a gate connected to a boost control signal, and a controlled current source coupled between a ground signal and the second node of the boost capacitor. In the write assist circuit, the boost capacitor has a discharge path which is controlled to provide a boost voltage which is invariant to a level of a power supply signal.

Static random access memory (SRAM) write assist circuit with improved boost

Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip.

Double-sided segmented line architecture in 3D integration

Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

Signal margin centering for single-ended eDRAM sense amplifier

Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.

Memory array with on and off-state wordline voltages having different temperature coefficients

Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.

Multi-bank random access memory structure with global and local signal buffering for improved performance

A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

Timer lockout circuit for synchronous applications

Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate 'n' sets of CAD information which are then time-multiplexed to the embedded memory at a speed 'n' times faster than the BIST operating speed.

Command multiplier for built-in-self-test

A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

Method and structure for enabling a redundancy allocation during a multi-bank operation

A SDRAM mid a tinier lockout circuit. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and a circuit for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage (&ldquo;V &rdquo;) monitor, a wordline on voltage (&ldquo;V &rdquo;) generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage (&ldquo;V &rdquo;) generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

Wordline on and off voltage compensation circuit based on the array device threshold voltage

A DC analog circuit which monitors a DRAM sample cell access device and outputs a DC reference voltage to the word line voltage regulation system. The resulting output voltage V from the word line voltage regulation system will then vary in accordance with the cell access device parametrics so as to guarantee a full high level will always be written into the DRAM cell.

Growing community of inventors

Colchester, VT, United States of America

Mark David Jacunski