Video Gaming Technologies, Inc.

Infineon Technologies Richmond, LP

Mark Daniel Eubanks

Jeremy Michael Webb

Steve Nicodemus

Sarah Jean Gozdecki

Richard Kerr Sisson

Keith Jordan White

Joerg Volrath

A gaming machine includes a processor and a presentation device coupled to the processor. The processor is programmed to determine that a free play trigger condition is satisfied, and to execute one or more free plays based on the free play trigger condition to create one or more free play outcomes. Each free play outcome is a winning free play outcome or a non-winning free play outcome. The presentation device is configured to present winning free play outcomes when at least one free play outcome is a winning free play outcome. Non-winning free play outcomes are not presented.

Gaming machines with free play bonus mode presenting only winning outcomes

A method according to the present invention is provided for determining memory device identification. The method invokes a serial output from n identification fuses of two or more memory devices, the output for identifying the device, and sampling the serial output every n bit to determine a fuse state for a fuse of each device. The method further repeats the sampling for all n fuses to acquire fuse data for all devices, and determines a pass/fail string corresponding to the sampled output, the pass/fail string being employed to identify the devices through a parallel test and burn-in system. The output is on an enabled data line which is used during the burn-in test wherein other data lines are disabled for avoiding bus contention. The method also includes storing the pass/fail string for the data in a database, and translating the pass/fail string using a structured query language expression executed against the database.

Method for reading semiconductor die information in a parallel test and burn-in system

A memory system on a semiconductor body is tested by testing components formed on the semiconductor body. A programmable clock signal generator receives an external clock signal and selectively generates an output clock signal having a frequency at a predetermined multiple of the received external clock signal. A counter receives the output clock signal from the clock signal generator and generates output signals having a cyclical binary count up to the predetermined multiple of the received external clock signal. Memory locations in a programmable look-up memory store separate commands for testing the memory system. The programmable look-up memory receives each of selective remotely generated binary encoded address signals to access a separate predetermined look-up memory section, and the binary output signals from the counter for sequentially accessing separate memory locations within the separate predetermined look-up memory section.

On-chip circuits for high speed memory testing with a slow memory tester

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Mechanicsville, VA, United States of America

Mark Daniel Eubanks