Intel Corporation

Mark D Winston

Steven E Wells

Virgil N Kynett

Owen W Jungroth

Jerry A Kreifels

Richard D Pashley

Alan E Baker

George Hoekstra

George A Kosonocky

Robert N Hasbun

Jahanshir J Javanifard

Mark E Bauer

Rodney R Rozman

Mamun Ur Rashid

Johnny Javanifard

Sherif R Sweha

David M Brown

Marc E Landgraf

David J Kaplan

George Blanchard

Glen Hawk

Gary J Gallagher

An integrated circuit (IC) memory device having an interface coupled with a volatile random access memory (RAM) array and a nonvolatile flash memory array. Data to be written from an external device to the IC memory device is initially written to the volatile RAM array to provide for fast execution of a write operation, and is then written from the volatile RAM array to the nonvolatile flash memory array via the interface in a manner that is relatively transparent to external devices and the user. The interface may be configured to transfer data from the volatile RAM array to the external device if a read request matches an address tag field stored in the volatile RAM array. Data from first and second block addresses in the volatile RAM array and flash memory array may be merged in a flash merge buffer, and validity bits may be used to ensure that potentially stale data in the flash memory array is not used and that data coherency is maintained. Data may also be simultaneously written to or read from the volatile RAM array during at least a portion of the time in which data is being read from or written to the flash memory array. A check may be made to ensure that the flash merge buffer is empty before reading data from the flash memory array.

Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array

A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Method and circuitry for usage of partially functional nonvolatile memory

A nonvolatile memory includes a global line. A plurality of memory blocks and a redundant block are also included in the memory, each block having a plurality of local lines and a decoder for selectively connecting the global line to one of the local lines when the decoder is enabled and for isolating the local lines from the global line when the decoder is disabled. When one of the plurality of blocks is found to be a defective block, the defective block is replaced by the redundant block. Circuitry is provided for disabling the decoder of the defective block and enabling the decoder of the redundant block whenever the defective block is addressed.

Nonvolatile memory blocking architecture and redundancy

A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern. The arrangement allows the simplest forms of error detection and correction circuitry to be utilized.

Generally-diagonal mapping of address space for row/column organizer

A microprocessor system includes a central processing unit (CPU) and a nonvolatile memory having a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. A multiplexer has inputs coupled to the first memory array and the second memory array for selectively coupling one of the first memory array and the second memory array to an output of the memory. The array select circuitry directs the first address to the first memory array and the second address to the second memory array. The array select circuitry controls the multiplexer to couple the second memory array to the output during the reprogramming operation of the first memory array. The memory further includes a write state machine for controlling reprogramming of the memory. The write state machine allows write automation of the nonvolatile memory.

Microprocessor system including first and second nonvolatile memory

A method for writing data to an entry in a portion of a flash EEPROM memory array during a period in which that portion of the array is being erased and writing is prohibited. The method includes writing the data to a new entry position apart from the portion of the array which is being erased along with a revision number which is greater than the revision number of the original data in the original portion of the array, writing of the busy condition of the original entry to a temporary storage position apart from the portion of the array which is being erased, and invalidating entries listed in the temporary storage position when the erase operation is concluded.

Method for writing to a flash memory array during erase suspend intervals

A detection circuit is described that resides in a nonvolatile memory that includes a memory array and a control circuitry coupled to the memory array for controlling operations of the memory array. The detection circuit is coupled to the control circuitry and receives a power supply for detecting potential level of the power supply and for generating a reset signal to reset the control circuitry until the potential level of the power supply rises above a predetermined level. The detection circuit includes a resistor, a first, a second, and a third transistor. The first transistor has a first end coupled to receive the power supply, a second end coupled to a first node, and a third end coupled to the first node. The second transistor has a first end coupled to the first node, a second end coupled to ground, and a third end coupled to the ground. The first and second transistors function as a voltage divider. The third transistor has a first end coupled to the power supply, a second end coupled to an output node, and a third end coupled to the first node. The resistor is coupled between the output node and the ground for coupling the output node to the ground when the third transistor is not conducting, and for providing a positive potential at the output node when the third transistor is conducting. When the power supply has not reached the predetermined level, the third transistor is not conducting and the output node outputs the reset signal that is a ground potential. When the power supply rises above the predetermined level, the third transistor starts to conduct and the output node registers the positive potential and ceases generating the reset signal. The first, second, and third transistors are of the same channel type such that the circuitry operates substantially independent of process variations and temperature variations.

Circuitry for power supply voltage detection and system lockout for a

A floating gate nonvolatile memory. The memory includes a first memory array and a second memory array. A first address register is provided for storing a first address for the first memory array. A second address register is provided for storing a second address for the second memory array. A multiplexer is coupled to the first memory array and the second memory array at one end and an output of the memory device at the other end for selectively coupling one of the first memory array and the second memory array to the output at a time. Array select circuitry responsive to an incoming address is provided for selecting the first memory array for a reprogramming operation and the second memory array for a read operation. The array select circuitry directs the first address to the first address register and the second address to the second address register. The array select circuitry controls the multiplexer for coupling the second memory array to the output during the reprogramming operation of the first memory array.

Floating gate nonvolatile memory with reading while writing capability

A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.

Processor controlled command port architecture for flash memory

A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.

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El Dorado Hills, CA, United States of America

Mark D Winston