International Business Machines Corporation

Mark D Sweet

Richard G Fogg, Jr

Cang Ngoc Tran

Harrell Hoffman

Gerald Bernard Long

Dac C Pham

Circuitry within a processor delays the launching of data onto an external bus by a factor that is proportional to the ratio of an internal processor clock speed to the system or external bus clock speed. This delay provides a delay in the launching of data to external bus devices so that these slower speed external bus devices have enough time to capture the data.

Apparatus for delaying the output of data onto a system bus

A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.

Interface for logic simulation using parallel bus for concurrent

A system and method for managing service requests from peripherals connected to a personal computer or workstation by operating both in an interrupt mode and a polling mode, with selective transition therebetween. In one practice of the invention, peripheral device service requests are first managed on an interrupt basis, then transition to a polling mode when the interrupt rate exceeds a rate threshold, and subsequently revert back to the interrupt mode when the rate again decreases below a threshold. The transition is dynamic and situation adjustable by parameter selection both as to the number of service requests and as to the time interval used to initiate transition between the interrupt and polling modes.

System and method for dynamically varying between interrupt and polling

An all events trace gatherer for a logic simulation machine is disclosed. The all events trace gatherer generates an all events trace (AET) which is a record of what has happened to all or a subset of the facilities by monitoring a simulation bus on which the logic simulation machine put a calculated result during the simulation thereon. The AET gatherer allows an AET to be gathered without slowing the simulation. The AET gatherer is an auxiliary processor that is connected to the simulation bus in the logic simulation machine in parallel with simulation processors of the machine.

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Austin, TX, United States of America

Mark D Sweet