Packard Bell Nec

Zenith Data Systems Corporation

Nec Corporation

Mark D Nicol

David T DeRoo

Robert A Kohtz

Michael P Krau

Saifuddin T Fakhruddin

Lloyd W Gauthier

David J DeLisle

Jimmy Dean Smith

Terence Paul O'Brien

Brian K Straup

Mark L Herman

Anthony M Olson

Richard D Ball

Todd R Witkowski

Jimmy D Smith

Gordon L Helm

Thomas N Robinson

Richard David Ball

Terrence A Hussey

William J McAuliffe

A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports. A common memory device is addressable by the processors, and responsive to the controller to share addressing of the common memory device.

Multiprocessor system for enabling shared access to a memory

The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost.

Expansion module including programmable chip selects

An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.

Protected address range in an electrically erasable programmable read

Programmably selectable addresses for expansion cards for a motherboard

A programmable hardware timer provides a relatively consistently measure of predetermined time intervals over a relatively wide range of performance levels. The programmable hardware timer includes a downcounter, driven by a predetermined clock frequency, that counts a preprogrammed number of preselected time intervals. The time intervals, also programmable, are written to registers which, in turn, are used to control the downcounter such that the zero flag on the downcounter goes active at the predetermined time interval. A second downcounter is used to enable multiples of the predetermined time interval to be selected.

Programmable hardware timer including two programmable hardware

A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoiding copying this already copied code and executing directly from the volatile memory considerable time is saved. Since BIOS code is typically on the order of 10K bytes, elimination of the necessity to rewrite BIOS and vectoring directly to BIOS image file in RAM saves on the order of ten thousand clock cycles.

Method for warm boot from reset

In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other critical systems data.

Method to store privileged data within the primary CPU memory space

The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the peripheral CPU(s). Additionally, for digital systems in which the peripheral CPU(s) cannot address the full range of the address space of the shared memory that is available to the CPU, the CPU can control the relocation of the block of code for the peripheral CPU(s) (i.e., provide a code paging system).

Apparatus to allow a CPU to control the relocation of code blocks for

Programmable hardware counter

The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Write once read only registers

System for establishing a transfer mode between system controller and

Write inhibited registers

Manual insertion of hardware jumpers to configure I/O device selection and addressing is eliminated through the implementation of specialized hardware which allows for program control over several addressing paths. A register file is utilized within a programmable device to configure demultiplexers and multiplexers which map I/O address control line signals to set up various communication paths for address I/O exchanges. I/O configuration is entirely removed from add-on cards through the use of the programmable device. Accordingly, such add-on cards only require minimum circuitry, thus facilitating the use of miniature or baby cards as option cards which are much smaller than standard add-on cards.

Apparatus for selecting a user programmable address for an I/O device

Growing community of inventors

Stevensville, MI, United States of America

Mark D Nicol