Aristos Logic Corporation

Mark D Myran

Robert L Horn

Virgil V Wilkins

Gnanashanmugam Elumalai

David S Walls

A transaction processor pipeline architecture and associated apparatus for processing multiple queued transaction requests incorporates multiple processing elements working in parallel. Each processing element is configured to perform a specific function within the transaction processor system. Certain processing elements are assigned as function controllers, which are assigned to process specific transaction request subtask categories and may be augmented with dedicated hardware to accelerate certain subtask functions. Other processing elements are configured as list managers, which are optimized for managing data structure operations in memory. The processing elements are connected by a cross-point interconnect. The transaction processor system is configurable and scalable based on application needs.

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Aliso Viejo, CA, United States of America

Mark D Myran