International Business Machines Corporation

Mark D Mayo

Ruchir Puri

Paul Gerard Villarrubia

Brian William Curran

Shyam Ramji

Prabhakar Nandavar Kudva

Wilhelm Ernst Haller

Ricardo H Nigaglioni

Sean Michael Carey

Yiu-Hing Chan

Reinaldo A Bergamaschi

David A Kiesling

Arnold E Barish

Hartmut Sturm

Matthew E Mariani

Walter A Svarczkopf

Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets.

Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit

A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network () comprises two carry lookahead trees () working in parallel to each other, wherein a first carry lookahead tree () provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree () provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.

Carry-select adder structure and method to generate orthogonal signal levels

A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.

Logic block timing estimation using conesize

A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors. The third transistor has its first terminal connected to the circuit node, its second terminal connected to the selected resistor, and its control terminal connected to sense the potential at the other of the resistors. The circuit functions to sense the potential difference between the first and second differential output signals. When the potential difference is less than a predetermined level, a second current is sunk through the one resistor so as to lower the potential of the output signal associated with the one resistor relative to the potential of the output signal associated with the other resistor.

Method and apparatus for detecting faults in differential current

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Wappingers Falls, NY, United States of America

Mark D Mayo