International Business Machines Corporation

Mark D Marik

Todd Weston Arnold

Elizabeth A Dames

Clarence Harrison

Roger L Posthumus

Richard Victor Kisley

Michael James Kelly

Carsten D Frehr

Kurt S Jacobsen

Jesper Wiese

Tamas Visegrady

Michael D Hocker

Michael J Miele

Susan E Waefler

Jimmie Ray Mayfield

Surya V Duggirala

Robert A Palo

Michael Ordway Tingey, Jr

A method, a computer program product, and a system are provided that handles host requests on a hardware security module (HSM). The method includes selecting a domain with a longest wait time with a host request for the HSM and selecting an oldest host request requested by the domain. The method also includes determining a hardware engine type required to process the oldest host request and determining a saturation level of the hardware engine type exceeds a saturation threshold. The method further includes selecting a second host request requested by the domain that uses a different hardware engine type based on the saturation level exceeding the saturation threshold and processing the second host request using the different hardware engine type of the HSM. The method further includes selecting unprocessed host requests of the domains to continuously provide efficient selection of those host requests to the HSM.

Smart round robin delivery for hardware security module host requests

Embodiments include method, systems and computer program products for secure logging of host security module. In some embodiments, an event may be received. The event may include data to be written to a secure log file. A hash may be generated using data of the event. The hash may be stored in a first field of an event record associated with the event. The event record may be stored in the secure log file. The hash may be stored in a second field of a next event record in the secure log file.

Secure logging for host security module

An aspect of cipher text translation includes a memory configured to store predetermined conditions for performing an encryption operation, and a processor communicatively coupled to the memory. The processor is configured to execute computer readable instructions. The computer readable instructions include determining through analysis of an inbound key and an outbound key of the encryption operation that the encryption operation includes a translation from a first class of encryption to a second class of encryption. The second class of encryption is determined to be weaker than the first class of encryption. The instructions also include applying the predetermined conditions to the input key and the output key and authorizing the translation via the processor, based on the applying, when aspects of the predetermined conditions are satisfied.

Cipher text translation

A computer system includes memory configured to store information regarding predetermined conditions of an encryption operation and a processor configured to analyze an inbound key and an outbound key of the encryption operation. The processor is also configured to determine that the encryption operation includes a translation from a first class of encryption to a second class of encryption based on the analyzing the inbound key and the outbound key, and to determine whether the translation is permitted based on the predetermined conditions.

Providing concurrent embedded application updates comprising a first computer processor for executing a first embedded application, the executing generating a first plurality of processing threads, the first computer processor coupled to a first storage location and a second storage location. The first computer processor configured to accept and process instructions from a host system, receive one or more notifications indicating that a second embedded application has been successfully loaded into one of the first storage location and the second storage location, terminate execution of the first plurality of processing threads in response to receiving the one or more notifications, and execute the second embedded application while continuing to accept instructions from the host system and without restarting in response to receiving the one or more notifications.

Concurrent embedded application update

A method, article, and system for providing an effective implementation of a data structure comprising instructions that are cryptographically protected against alteration or misuse, wherein the instructions further comprise a trusted block that defines specific key management policies that are permitted when an application program employs the trusted block in application programming interface (API) functions to generate or export symmetric cryptographic keys. The trusted block has a number of fields containing rules that provide an ability to limit how the trusted block is used, thereby reducing the risk of the trusted block being employed in unintended ways or with unintended keys.

Method for improved key management for ATMs and other remote devices

A method, article, and system for providing an effective implementation of data structures, and application programming interface (API) functions that allow secure execution of functions behind a secure boundary. The controlling mechanism is a flexible, extendable, and non-forgeable block that details how values and parameters behind the secure boundary can be changed. The invention allows for one entity to execute a security function that will normally require extensive authorizations or dual or multiple control. The method and system comprise instructions that are cryptographically protected against alteration or misuse, wherein the instructions further comprise a trusted block that defines security policies that are permitted when an application program employs the trusted block in APIs. The trusted block has a number of fields containing rules that provide an ability to limit how the trusted block is used, thereby reducing the risk of the trusted block being employed in unintended ways.

Method for controlling security function execution with a flexible, extendable, and non-forgable block

A method and apparatus for handling an interrupt from a real-time clock to increment a program clock in a computer system while compensating for missed interrupts due to contention on a system bus from a DMA controller or the like. In accordance with the invention, a count is stored representing a cumulative interval of time that has elapsed without a corresponding incrementing of the program clock. In response to an interrupt from the real-time clock, the processor transfers control to an interrupt handling routine, which determines the interval of time that has elapsed since the previous real-time clock interrupt and increments the cumulative interval of time by the actual interval of time that has elapsed since the previous real-time clock interrupt. If the cumulative interval of time is greater than an expected interval of time between real-time clock interrupts, the interrupt handling routine iteratively increments the program clock and decrements the cumulative interval of time to reflect incrementing of the program clock until the cumulative interval of time is less than the expected interval of time between real-time clock interrupts.

Method and apparatus for handling an interrupt from a real-time clock to increment a program clock

A remote program monitor method and system using a system-under-test microcontroller for self-debug comprises a system-under-test (SUT) that includes a read-only memory (ROM) and a microcontroller for executing a program under test. The microcontroller has an interrupt input, wherein one or more enable debugger signals received at the interrupt input causes the microcontroller to execute a debugger program contained in the ROM. The SUT is connected with a host computer over a standard serial connection. When the SUT receives one or more debugger signals as an interrupt input, the signal causes the microcontroller to execute a debugger program contained in the ROM.

Remote program monitor method and system using a system-under-test

An apparatus and method for communicating information between a computer and a plurality of peripherals along a plurality of communication channels is disclosed. The computer and peripherals are connected in a succession of stages (cascaded), in a tree-like (hierarchical) communication network configuration. Peripherals in the network include an associated communication unit which is responsible for transmitting and/or receiving data communicated on a communication channel. The communication unit facilitates the transfer of data to, and the receipt of data from, the unit's parent, and also facilitates the transfer of data to, and the receipt of data from, any child units. In the invented method, each communication unit, in parallel, composes those individual messages received from child units into a single composite message and transmits the composite message to the communication unit's parent. The parent, in turn, composes those individual or composite messages it has received into a single composite message and transmits the contents to its parent. This continues until a single composite message is transmitted to the computer for processing. The computer decomposes a composite message into its constituent individual messages and processes individual messages. The computer can also transmit messages to peripherals in a reciprocal manner, that is, by composing a single composite message to be transmitted to the first stage communication unit and thereafter decomposed and distributed to designated nodes within the network.

Apparatus and method for data communication between nodes

A two-frequency data signal, also known as a biphase or F/2 F signal, is accurately decoded by sampling the signal and digitizing the samples to provide a series of digital values representing the signal. An intelligent digital filter manipulates the digital values to decode the signal, by detecting the peaks in the sampled signal and decoding the signal by analyzing the location and amplitudes of the peaks. Only peaks which are outside a guard band may be detected. If the signal cannot be properly decoded with a wide guard band, the guard band may be repeatedly narrowed, until a minimum guard band is reached. Bits are identified by comparing the displacements between peaks to a bit cell width. An even number of displacements indicates a `0` bit, and an odd number of displacements indicates a `1` bit. After decoding, the bits are converted into bytes. Parity and longitudinal redundancy code checks are used to correct bad bits. During decoding, many indications of a degraded signal may be obtained. If a degraded signal is indicated, the host computer is notified, even though the signal was properly read. Card replacement can then be initiated at the first signs of signal degradation, before the data signal becomes unreadable.

Apparatus for decoding degraded data signals

A two-frequency data signal, also known as a biphase or F/2F signal, is accurately decoded by sampling the signal and digitizing the samples to provide a series of digital values representing the signal. An intelligent digital filter manipulates the digital values to decode the signal, by detecting the peaks in the sampled signal and decoding the signal by analyzing the location and amplitudes of the peaks. Only peaks which are outside a guard band may be detected. If the signal cannot be properly decoded with a wide guard band, the guard band may be repeatedly narrowed, until a minimum guard band is reached. Bits are identified by comparing the displacements between peaks to a bit cell width. An even number of displacements indicates a `0` bit, and an odd number of displacements indicates a `1` bit. After decoding, the bits are converted into bytes. Parity and longitudinal redundancy code checks are used to correct bad bits. During decoding, many indications of a degraded signal may be obtained. If a degraded signal is indicated, the host computer is notified, even though the signal was properly read. Card replacement can then be initiated at the first signs of signal degradation, before the data signal becomes unreadable.

Method and apparatus for decoding two frequency (f/sf) data signals

A two-frequency data signal, also known as a biphase or F/2F signal, is accurately decoded by sampling the signal and digitizing the samples to provide a series of digital values representing the signal. An intelligent digital filter manipulates the digital values to decode the signal, by detecting the peaks in the sampled signal and decoding the signal by analyzing the location and amplitudes of the peaks. Only peaks which are outside a guard band may be detected. If the signal cannot be properly decoded with a wide guard band, the guard band may be repeatedly narrowed, until a minimum guard band is reached. Bits are identified by comparing the displacements between peaks to a bit cell width. An even number of displacements indicates a `0` bit, and an odd number of displacements indicates a `1` bit. Once a bit is decoded, the bit cell width is incremented by a predetermined amount if the bit cell width is wider than the current bit cell width, and is decremented by a predetermined amount if the decoded bit cell width is narrower than the current bit cell width. If no peaks are found within a maximum allowable bit cell width, this area is delimited as bad. An attempt is made to decode the bits in the bad area by analyzing all peaks without regard to a guard band. After decoding, the bits are converted into bytes. Parity and longitudinal redundancy code checks are used to correct bad bits.

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Denver, NC, United States of America

Mark D Marik