Unisys Corporation

Mark D Luba

Philip C Bolyn

Anthony P Gold

Michael K Benton

Eric D Aho

A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.

Scalable memory controller

A memory controller is described that comprises individual control segments for controlling memory that is divided into individual pairs of memory segments. The programmable memory controller provides improved average access times for memory devices by reducing the number of wait cycles between memory operations. A common data bus is shared between the memory segments. Each control segment provides individual sets of address and control lines to each memory segment so that control sequences can occur simultaneously between multiple control and memory segments. Accordingly, when a control sequence is in process within one segment, another control sequence can occur simultaneously in another segment. By overlapping control sequences in this fashion, the bandwidth of the data bus is increased by remaining idle less frequently. Each control segment provides a plurality of allow mode signals to the other control segment. The allow mode signals are used by a request selector to select a memory request from a plurality of pending memory requests, such that the selected request can begin as soon as one of the control segments is ready to accept such a request.

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Plymouth Meeting, PA, United States of America

Mark D Luba