Mcnc

Astarix Inc.

The University of North Carolina at Chapel Hill

Mark D Kellam

Joseph Daniel Mis

Gretchen Maerker Adema

W Boyd Rogers

Stephen M Bobbio

Arnold Reisman

Farid M Tranjan

Thomas D DuBois

Susan K Jones

Charles Kenneth Williams

Gershon Kedem

Michele J Berry

Bruce W Dudley

Nandini Tandon

A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.

Solder bump fabrication methods and structures including a titanium barrier layer

A micro-relay module includes a substrate and a lid in spaced apart relation, and a solder ring which bonds the lid to the substrate to define a chamber therebetween. A micromachined relay is integrally formed on the substrate or on the lid within the chamber. A gas is contained in the chamber at a gas pressure which is above atmospheric pressure. Input/output pads are included outside the chamber and electrically connected to the micromachined relay. Large numbers of encapsulated modules may be fabricated on a single substrate by integrally forming an array of relays on a face of a first substrate. A second substrate is placed adjacent the face with a corresponding array of solder rings therebetween, such that a respective solder ring surrounds a respective relay. The solder rings are reflowed in a gas atmosphere which is above atmospheric pressure to thereby form an array of high pressure gas encapsulating chambers. The first and second substrates are then singulated for form a plurality of individual micro-relay modules.

Encapsulated micro-relay modules and methods of fabricating same

Thin layers of aluminum and palladium are deposited and annealed to produce aluminum-palladium alloy. The surface of the alloy is exposed and treated with an aluminum enchant to produce a catalytic surface. The catalytic surface is used for electroless plating of nickel, providing excellent plating uniformity and adhesion, as well as a reduced plating induction time. Several variants of the basic method are shown.

Aluminum-palladium alloy for initiation of electroless plating

Solder bump fabrication methods and structure including a titanium

A photoresist (18) is exposed through a design-independent high resolution reticle (20), producing a high resolution image of exposed resist (18A). Photoresist (18) is exposed for the second time through a design-specific low-resolution reticle (24), exposing selected portions (18D) of previously unexposed resist. The remaining portions (18B) of previously unexposed resist form a design-dependent high resolution image. After development of photoresist (18), its unexposed portions (18B) are removed, producing openings (26) in photoresist (18), that can be transferred to underlying material (36), for example by etching openings in that underlying material (36), thereby transferring the design-dependent high-resolution image to it. Since the design-independent high resolution reticle (20) can be prefabricated ahead of time and used to produce many designs with different functions, the above double-exposure method is suitable for fabricating design-specific high resolution features, e.g., contacts (vias) between conducting layers, within time and at the approximate cost required to fabricate and process a low resolution image. Several variants of the basic method are possible.

High resolution mask programmable via selected by low resolution

Thin layers of aluminum (13) and palladium (12) are deposited and annealed to produce aluminum-palladium alloy (14). The surface of the alloy (14) is exposed and treated with an aluminum etchant to produce a catalytic surface (15). The catalytic surface is used for electroless plating of nickel, providing excellent plating uniformity and adhesion, as well as a reduced plating induction time. Several variants of the basic method are possible.

A field effect transistor includes a pair of buried centroid regions in a semiconductor substrate at a predetermined depth from the substrate face and having a doping concentration opposite the source and drain regions. A gradient region surrounds each of the pair of buried centroid regions. The gradient regions have decreasing doping concentration in all directions away from the associated centroid region. Source and drain extension regions may also be provided. The buried centroid/gradient regions operate to screen charge on the source and drain regions facing the channel to prevent this charge from interacting with the channel. Short channel effects are thereby reduced or minimized. The threshold voltage of the device can also be adjusted without the need for threshold adjusting implants. The buried centroid/gradient regions and source and drain extension regions may be fabricated in a self-aligned process using the gate and gate sidewall spacers as a mask.

Self-aligned charge screen (SACS) field effect transistors and methods

An electrically and mechanically robust microelectromechanical transducer is formed of a pleated dielectric sheet having patterned electrical conductors on the opposing faces thereof. The pleats define a plurality of spaced apart walls, with each wall including an electrically conductive portion at one side thereof. Positive and negative voltages, applied to opposite faces of the pleated sheet, cause the walls to move towards one another by electrostatic attraction. The walls can also move away from one another by electrostatic repulsion upon application of appropriate voltages. The microelectromechanical transducer may be fabricated by fabricating a sheet with integral pleats or by forming a 'self-pleating' flat sheet which forms pleats after conductor fabrication thereon.

Pleated sheet microelectromechanical transducer

An electroluminescent display device including a semiconductor substrate having a phosphor layer on one face thereof, and a space charge removing means in the semiconductor substrate. The space charge removing means continuously removes carriers, typically electrons, from the space charge barrier region formed during device operation, to thereby reduce space charge barrier related brightness limitations. The space charge removing means may comprise a doped region in the semiconductor substrate adjacent the phosphor layer, which is DC biased to continuously remove electrons from the space charge region. Alternatively, the doped region in the substrate adjacent the phosphor layer may inject electrons into the phosphor layer, with space charge removal being accomplished by a DC biased substrate contact. The space charge region in the substrate is reduced or eliminated thereby increasing the maximum number of electrons which can be injected into the electroluminescent layer and increasing the brightness of the display device.

Electroluminescent display with space charge removal

A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without 'bird's beak' formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.

Growing community of inventors

Chapel Hill, NC, United States of America

Mark D Kellam