Motorola Corporation

Freescale Semiconductor,inc.

Mark D Griswold

Robert Bruce Davies

James David Burnett

Frank K Baker

Richard D Sivan

Vida Ilderem

Diann M Dow

Juan Buxo

Jennifer H Morrison

Anthony Ciancio

James D Paulsen

Amudha R Irudayam

Shane R Chilton

Iksung Lim

James E Prendergast

Harrison B Haver

By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.

Semiconductor device and making thereof

An insulated gate field effect transistor (10) having an reduced gate to drain capacitance and a method of manufacturing the field effect transistor (10). A dopant well (13) is formed in a semiconductor material (11). A gate oxide layer (26) is formed on the dopant well (13) wherein the gate oxide layer (26) and a gate structure (41) having a gate contact portion (43) and a gate extension portion (44). The gate contact portion (43) permits electrical contact to the gate structure (41), whereas the gate extension portion (44) serves as the active gate portion. A portion of the gate oxide (26) adjacent the gate contact portion (43) is thickened to lower a gate to drain capacitance of the field effect transistor (10) and thereby increase a bandwidth of the insulated gate field effect transistor (10).

Insulated gate semiconductor device and method of manufacture

A semiconductor device (8) has an insulating layer (16) overlying a semiconductor substrate (12). The insulating layer has a first opening that defines an aperture (18) extending from the insulating layer to the semiconductor substrate, and at least a first portion of a first conductive terminal (42) is disposed in the aperture. A second conductive terminal (52) has a second portion (28) disposed in the aperture. The second portion of the second conductive terminal is separated from the first conductive terminal by a composite dielectric layer including a nitride layer (32) and an oxide layer (30). In one approach, the oxide layer is formed by the oxidation of the second portion of the second conductive terminal.

Semiconducter device having an emitter terminal separated from a base

A method and apparatus is provided for removing metallic contamination from a fluid or liquid that passes through a recirculating system (10) that is used for cleaning and etching semiconductor wafers. A bath 11) and fluid is provided. A recirculared fluid flows through a silicon media, thereby removing the metallic contamination from the liquid. In a preferred embodiment, the silicon media is a plurality of silicon or polysilicon beads which provide a maximum surface area in a minimum of space. Additionally, removal of metallic contamination from the recirculating fluid is combined with particle filtration of the recirculating fluid single housing.

Apparatus and method for removing metallic contamination from fluids

A method for forming high quality oxides wherein semiconductor material is placed in an oxidizing environment and subjected to a predetermined concentration of oxygen. This oxygen concentration is increased over time until a predetermined amount of oxide has been formed. Once the predetermined amount of oxide has been formed, the semiconductor material/oxide interface is subjected to a burst of steam that passivates the interface thereby reducing the number of unreacted semiconductor material atoms.

Ramped oxide formation method

A new and improved method using the deposition of amorphous silicon for the formation of semiconductor memory device interlevel dielectrics. After the deposition of a first polysilicon layer, an amorphous silicon layer is deposited thereon. The polysilicon layer and amorphous silicon layer are etched to form a floating gate. The amorphous silicon layer allows for the growth of thermal oxide layers to take place at lower temperatures thereby decreasing the temperature at which the oxide layers are grown while still repressing the asperity formation. This allows for high quality oxide insulation layers.

Deposition of amorphous silicon for the formation of interlevel

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Chandler, AZ, United States of America

Mark D Griswold