International Business Machines Corporation

Mark D Aubel

Zhuo Li

Charles Jay Alpert

Chin Ngai Sze

Jeanne P Bickford

Paul Gerard Villarrubia

Howard Smith Landis

Natarajan Viswanathan

Mark Steven Styduhar

Charles H Windisch, Jr

Gregory F Ford

Michael T Ross

Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.

Boundary latch and logic placement to satisfy timing constraints

Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes. Optionally, each hybrid fill-placeable library element comprises different fill shapes at different levels and corresponding to different features so that it can be employed to meet multiple different density rules.

Method and system allowing for semiconductor design rule optimization

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Essex Junction, VT, United States of America

Mark D Aubel