Rockwell Collins, Inc.

Mark Clifford Singer

Mark A Kovalan

Douglas Robert Johnson

John W Roltgen

Douglas L Bader

James E Sisson

Samir S Hemaidan

James J Corcoran

Eric J Danielson

John William Roltgen, Iii

Zafar S Ahmad

A system includes a first plurality of processors, a second plurality of processors dissimilar from the first plurality of processors, a first arbitration device coupled to the first plurality of processors, and a second arbitration device coupled to the second plurality of processors. The first arbitration device and the second arbitration device is configured to receive event data, store the received event data, and to output the received event data at substantially a same time. At least one processor of the first plurality of processors and at least one processor of the second plurality of processors are configured to access the event data.

Synchronization mechanisms for high-integrity computing

A control system for an aircraft including first and second lanes having respective first and second processors dissimilar to one another and configured to output respective first and second computation data. At least one programmable logic device may be configured to receive the first computation data output and the second computation data output, determine a difference therebetween, and transmit a corrective computation data output to the first processor and the second processor via respective feedback loops if the difference between the first computation data output and the second computation data output exceeds a predetermined threshold value.

System and method for maintaining system integrity in control systems having multi-lane computational differences

A method for testing processors includes generating, from a set of input bits, a first set of machine data bits in a first processor and a second set of machine data bits in a second processor dissimilar to the first processor, and comparing the first and second sets of machine data bits to output a first comparison result. The method also includes generating, from a third set of machine data bits, a first and second sets of machine result bits, and comparing the first and second sets of machine result bits to output a second comparison result. The method further includes generating, from a fourth set of machine data bits, a first and second sets of output bits, and comparing the first and second sets of output bits to output a third comparison result. The method also includes determining whether the first and second processors operate substantially similar to each other based on at least one of the first, second, and third comparison results.

Method for testing capability of dissimilar processors to achieve identical computations

A system and method are provided for controlling aircraft flight control surfaces. The system may include at least three pilot sensor channels, each pilot sensor channel including a set of pilot sensor data. The system may also include at least three aircraft sensor channels, each aircraft sensor channel including a set of aircraft sensor data. The system may further include an actuator control component configured to synchronously receive and vote on the pilot sensor data and the aircraft sensor data, such that a voted output of the at least three pilot sensor channels is transmitted to a flight control computer and augmented before being transmitted to remote electronics units. The voted output of the at least three pilot sensor channels providing for the control of the aircraft surfaces coupled to the remote electronics units.

Triplex cockpit control data acquisition electronics

A flight control system includes an output device, a first processor, and a second processor. The second processor is dissimilar to the first processor. The flight control system also includes a first arbitration device coupled to the first processor and a second arbitration device coupled to the second processor. The second arbitration device is configured to coordinate transaction synchronization with the first arbitration device and the first arbitration device is configured to coordinate transaction synchronization with the second arbitration device. A comparator processor is coupled to the first arbitration device and the second arbitration device. The comparator processor is configured to compare transaction synchronized outputs of the first and second processors and the comparator processor effectuates a command to the output device if the comparison is valid.

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Cedar Rapids, IA, United States of America

Mark Clifford Singer